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| 1 ? HMP8117 ntsc/pal video decoder the HMP8117 is a high quality ntsc and pal video decoder with internal a/d converters. it is compatible with ntsc m, pal b, d, g, h, i, m, n, and combination n (n c ) video standards. both composite and s-video (y/c) input formats are supported. a 2-line comb filter plus a user-selectable chrominance trap filter provide high quality y/c separation. user adjustments include bright ness, contrast, saturation, hue, and sharpness. vertical blanking interval (vbi) data, such as closed captioning, wide screen signalling and teletext, may be captured and output as bt. 656 ancillary data. closed captioning and wide screen signalling information may also be read out via the i 2 c interface. the videolyzer ? feature provides approved macrovision ? copy-protection bypass and detection. features ? (m) ntsc and (b, d, g, h, i, m, n, n c ) pal operation - optional auto detect of video standard - itu-r bt.601 (ccir601) and square pixel operation ? videolyzer feature - macrovision? bypass and detection ? digital anti-alias filter ? power down mode ? digital output formats - vmi compatible - 8-bit, 16-bit 4:2:2 ycbcr - 15-bit (5,5,5), 16 -bit (5,6,5) rgb - linear or gamma-corrected - 8-bit bt.656 ? analog input formats - three analog composite inputs - analog y/c (s-video) input ? ?raw? (oversampled) vbi data capture ? ?sliced? vbi data capture capabilities - closed captioning - widescreen signalling (wss) - bt.653 system b, c and d teletext - north american broadcast teletext (nabts) - world system teletext (wst) ? 2-line (1h) comb filter y/c separator ?fast i 2 c interface applications ? multimedia pcs ? video conferencing ? video compression systems ? video security systems ? lcd projectors and overhead panels ? related products - ntsc/pal encoders: hmp8156, hmp8170 ordering information part number temp range ( o c) package package no. HMP8117cn 0 to 70 80 ld pqfp q80.14x20 hmpvideval/isa evaluation board: isa frame grabber notes: 1. pqfp is also known as qfp and mqfp. 2. evaluation board descriptions ar e in the applications section. data sheet september 2003 fn4643.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved. all other trademarks mentioned are the property of their respective owners. n o t r e c o m m e nd e d f o r n e w d e s i g n s n o r e c o m m e n d e d r e p l ac e m e nt c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
2 HMP8117 functional block diagram adc cvbs1 cvbs2 cvbs3(y) y in reset microprocessor interface and control input sample rate converter external anti-alias filter vbi detection & decoding logic intreq sa scl scl input clamp, mux, coarse agc, dc-restore y out see analog front end block diagram lcap external anti-alias filter coarse agc dc-restore ccap c fine agc, dc-restore control adc yin[7:0] cin[7:0] y/c separation output sample rate converter and user adjusts output data and timing fifo hsync vsync field dvalid vbivalid p[15:0] blank see digital processing block diagram sync-tip, backporch timing macrovision detect composite/luma chroma 3 HMP8117 analog front end block diagram lcap m u x 1.0 f vid1 vid2 y_in 1.0 f 1.0 f clamp clamp 75 7 6 5 cvbs2 cvbs1 cvbs3(y) 1.75v 2x 76 0.1 f 100 a 100 a charge pump 9 external anti-alias filter 8 10-bit adc 10 sync-tip enable digital anti- alias 13-step variable attenuator filter 8-bit y out y[7:0] y in low-pass filter (remove fsc) gain correction logic backporch enable gain control set point fine adjust mult. factor correction multiplier disable 11 4 storage cap buf chroma atten chroma atten (below) ccap 2x 29 c_in 1.0 f c 19 75 external anti-alias filter 17 10 a/d_test buf discharge charge 100 a 100 a charge pump discharge charge bias/ internal reference 0.1 f storage cap 1.0 f 78 28 rset ref_cap 12.1k c[7:0] # decoder pin # mux select digital anti- alias filter disable luma dc-restore logic chroma dc-restore logic chroma mult. (below) chroma mult. (offset luma signal to lower adc ref ~= 1.5v) (offset chroma signal to adc mid-scale ~= 2.0v) correction multiplier 7 nominal (ntsc) operating condition 6 5 cvbsx. size = input. sync tip clamped at ~= 1.75 vdc. 8 y out /y in . size = ~1.0 v p-p , sync tip offset ~= 1.5 vdc. pin # 19 c. size = input size. porch offset ~= 2.0 vdc. 17 a/d_test. size ~= f(luma agc), porch offset ~= 2.0vdc. 9 chroma input 76 nominal (ntsc) o perating condition lcap. dc-signal offset ~= 2.4 vdc. 29 ccap. dc-signal offset ~= 2.4 vdc. pin # 28 rset. dc-signal offset ~= 1.2 vdc. 78 ref_cap. dc-signal offset ~= 2.5 vdc. 2.5v 1.5v 10-bit adc 2.5v 1.5v sync-tip enable truncate 8-bit truncate 1.75v (signal bias ~ 2.0v) 4 to 13 decoder 13 powerdown 75 75 13-step variable attenuator 1.75v to mux 50 a ref clamp 2.0v 1.0 f 75 # pin vaa input video nmos (internal clamp) (external) + - 4 digital processing block diagram y[7:0] c[7:0] m u x chroma line comb chroma demod chroma data u, v sharpness adjust standard select m u x chroma phase detector chroma pll nco 4fsc clock clk2 freq select (24.54, 27.0 or 29.5mhz) line locked pll loop hue adjust agc and adjust vsync detect input rate converter sample filter delay trap clk2 to 4fsc ratio vsync lock field and sync output rate converter sample line locked nco chroma pll loop filter horizontal and vertical sharpness adjust u/v to cbcr color space converter, color killer filter lp filter enable lp filter cbcr y vbi detection and decoding logic c, cvbs y luma data chroma saturation normal m u x select chroma filter status stripper, brightness and contrast adjust, rgb conversion to fifo output data and timing fifo hsync vsync field dvalid vbivalid p[15:0] blank timing data vbi status macrovision detect mv status HMP8117 5 introduction the HMP8117 is designed to decode baseband composite or s-video ntsc and pal signals, and convert them to either digital ycbcr or rgb data. in addition to performing the basic decoding operations, these devices include hardware to decode differen t types of vbi data and to generate full-screen blue, black and color bar patterns. digital plls are used to synchronize to all ntsc and pal standards. a chroma pll is used to maintain color lock for chroma demodulation while a line-locked pll is used to maintain vertical spatial ali gnment. the plls are designed to maintain lock in the presen ce of vcr head switches, vcr trick-mode and multi-path noise. the HMP8117 provides the videolyzer feature for macrovision (mv) copy-protection bypass and detection. external video processing before a video signal can be digitized the decoder has some external processing considerations that need to be addressed. this section discusses those external aspects of the HMP8117. analog video inputs the HMP8117 supports either three composite or two composite and one s-video input. three analog video inputs (c vbs 1-3) are used to select which one of three composite video sources are to be decoded. to support s-vid eo applications, the y channel drives the cvbs3(y) analog input, and the c channel drives the c analog input. the analog inputs must be ac-coupled to the video signals, as shown in the applications section. anti-alias filters although a 23 tap digital halfband anti-alias filter is provided for each a/d channel, an external passive filter is recommended for optimum performance. the digital filter has a flat response out to 5. 4mhz with an approximate -3db bandwidth of 6.3mhz using a 27mhz input clk2 sample rate. for the cvbsx inputs, the filter is connected between the yout and yin pins. for the c (chroma) input, the anti- alias filter should be connected before the c input. recommended filter configurations are shown on the reference schematic in figure 20. these filters have flat response out to 4.2mhz with an approximate -3db bandwidth of 8mhz. if upgrading from the hmp8115 or hmp8112a, the previous filter configurations may be used but with slightly degraded bandwid th. alternative higher or lower performance filters conf igurations may substituted. digitization of video prior to a/d conversion, the input signal is offset and scaled to known video levels. after digitization, sample rate converters and a comb filter are used to perform color separation and demodulation. a/d conversion each cvbsx video input channel has a video clamp circuit that is independent of pll timi ng. the input clamp provides a coarse signal offset to pos ition the sync tip within the a/d converter sampling range so that the agc and dc- restore logic can operate. a/d conversion video data is sampled at the clk2 frequency then processed by the input sample rate converter. the output levels of the adc after agc and dc rest oration processing are: agc and dc restoration the agc amplifier attenuates or amplifies the analog video signal to ensure that the blank level generates code 56 or 59 depending on the video standard. the difference from the ideal blank level of 56 or 59 is used to control the amount of attenuation or gain of the analog video signal. to obtain a stable dc reference for the agc, a digital low-pass filter removes the chroma burst from the input signal?s backporch. dc restoration positions the video signal so that the sync tip generates a code 0. the internal timing windows for agc and dc restoration are show in figure 3. the appropriate windows are automatically determined by the decoder when the input signal is auto-detected or manually selected. (m) ntsc (m, n) pal (b, d, g, h, i, n c ) pal white 196 196 black 66 59 blank 56 59 sync 0 0 figure 1. agc and dc restore internal timing video input dc restore agc HMP8117 6 input signal detection if no input video signal is det ected for 16 consecutive line periods, nominal video timing is generated for the previously detected or programmed vi deo standard. a maskable interrupt is provided for the condition of ?input signal loss? allowing the host to enable blue field output if desired. vertical sync and field detection the vertical sync and field detect circuit uses a low time counter to detect the vertical sync sequence in the video data stream. the low time counter accumulates the low time encountered during any sync pulse, including serration and equalization pulses. when the low time count exceeds the vertical sync detect threshold, vsync is asserted immediately. field is asserted at the same time that vsync is asserted. field is asserted low for odd fields and high for even fields. field is determined from the location in the video line where vsync is detected. if vsync is detected in the first half of t he line, the field is odd. if vsync is detected in the second half of a line, the field is even. in the case of lost vertical sync or excessive noise that would prevent the detection of vertic al sync, the field output will continue to toggle. lost vertical sync is declared if after 337 lines, a vertical sync period was not detected for 1 or 3 (selectable) successive fields as specified by bit 2 of the genlock control register 04 h . when this occurs, the plls are initialized to the acquisition state. y/c separation a composite video signal has the luma (y) and chroma (c) information mixed in the same video signal. the y/c separation process is responsible for separating the composite video signal into these two components. the HMP8117 utilizes a comb filter to minimize the artifacts that are associated with the y/c separation process. input sample rate converter the input sample rate converter is used to convert video data sampled at the clk2 rate to a virtual 4xf sc sample rate for comb filtering and color demodulati on. an interpolating filter is used to generate the 4xf sc samples as illustrated in figure 2. comb filter a 2-line comb filter, using a single line delay, is used to perform part of the y/c separation process. during s-video operation, the y signal bypasses the comb filter; the c signal is processed by the comb filter si nce it is an integral part of the chroma demodulator. during pal operation, the chroma trap filter should also be enabled for improved performance. since a single line store is used, the chroma will normally have a half-line vertical offset from the luma data. this may be eliminated, vertically aligning the chroma and luma samples, at the expense of vertical resolution of the luma. bit 0 of the output format register 02 h controls this option. chroma demodulation the output of the comb filter is further processed using a patented frequency domain transform to complete the y/c separation and demodulate the chrominance. demodulation is done at a virtual 4xf sc sample rate using the interpolated data samples to generate u and v data. the demodulation process decimates by 2 the u/v sample rate. output sample rate converter the output sample rate conver ter converts the y, u and v data from a virtual 4xf sc sample rate to the de sired output sample rate (i.e., 13.5mhz). it also vertically aligns the samples based on the horizontal sync information embedded in the digital video data stream. the output sample rate is determined by the input video standard and the selected rectangular/square pixel mode. the output pixel rate is 1/2 of the clk2 input clock frequency. the output format is 4:2:2 for all modes except the rgb modes which use a 4:4:4 output format. clk2 input the decoder requires a stable clock source for the clk2 input. for best performance, use termination resistor(s) to minimize pulse overshoot and reflections on the clk2 input. since chroma demodulation uses the virtual 4xf sc , any jitter on clk2 will be transferred as chrominance error on the output pixels. the clk2 clock frequency must be one of the valid selections from table 1 below based on the video standard and desired pixel mode. the clk2 should be derived from a stable clock source, such as a crystal. clk2 must have at least a 50ppm accuracy and at least a 60/40% duty cycle to ensure proper time incoming video samples time resampled video 4xf sc figure 2. sample rate conversion table 1. video standard clock rate selection summary video format valid clk2 frequencies (mhz) rectangular pixel mode square pix- el mode (m) ntsc, (m) pal 27.00 24.54 (b, d, g, h, i, n, n c ) pal 27.00 29.50 HMP8117 7 operation. use of a pll to generate a ?line locked? clk2 input based on the input video is not recommend. (see next section below.) cycle slipping and real-time pixel jitter the decoder?s digital pll allows it to maintain lock and provide high quality y/c separation even on the poorest quality input video signals. however, this architecture does not provide a ?line lock clock? output and should not be used as a timing master for direct interface to another video encoder in a system. since the decoder uses a fix ed clk2 input frequency, the output pixel rate must be periodically adjusted to compensate for any frequency error between clk2 and the input video signal. this output pixel rate adjustment is referred to as cycle slipping . since the decoder has an output data fifo, all cycle slippi ng can be deferred until the next horizontal blanking interval. this guarantees a consistent number of pixels during the active video region. due to cycle slipping, the output timing and data will exhibit a nominal real-time (line-to-line) pixel jitter of one clk2 period. although the sample rate converter maintains a 1/8 pixel vertical sample alignment, the output data must be routed to a frame buffer or video compression chip in order remove the effects of cycl e slipping. (the frame buffer or compression chip serves as a time base corrector.) by directly interfacing the decoder to a video encoder, the output video signal will directly re flect the real-time pixel jitter effects of the decoder output timing. the jitter effects can be visualized on a crt monitor usi ng a static image containing patterns with sharp vertical edges. the edges will appear more ?ragged? when compared to the input video signal. the severity of this visual effect relates directly to the frequency error between clk2 and the input video signal. it is nearly impossible to completely match clk2 with the input video signal. therefore, a direct decoder to encoder interface is not recommended. the use of an external pll to generate a ?line locked? clk2 input derived from the input video signal is also not recommended, since this will defeat the internal digital pll and result in pixel decoding errors. digital processing of video once the luma and chroma have been separated the HMP8117 then performs programmable modifications (i.e. contrast, coring, color space co nversions, color agc, etc.) to the decoded video signal. uv to cbcr conversion the baseband u and v signals are scaled and offset to generate a nominal range of 16-240 for both the cb and cr data. digital color gain control there are four types of color gain control modes available: no gain control, automatic gain control, fixed gain control, and freeze automatic gain control. if ?no gain control? is select ed, the amplitude of the color difference signals (cbcr) is not modified, regardless of variations in the color burst amp litude. thus, a gain of 1x is always used for cb and cr. if ?automatic gain control? is selected, the amplitude of the color difference signals (cbcr) is compensated for variations in the color burst amplitude. the burst amplitude is averaged with the two previous lines having a color burst to limit line- to-line variations. a gain of 0.5x to 4x is used for cb and cr. if ?fixed gain control? is select ed, the amplitude of the color difference signals (cbcr) is multiplied by a constant, regardless of variations in the color burst amplitude. the constant gain value is specified by the color gain register 1c h . a gain of 0.5x to 4x is used for cb and cr. limiting the gain to 4x limits the amount of amplified noise. if ?freeze automatic gain control? is selected, the amplitude of the color difference signals (cbcr) is multiplied by a constant. this constant is the value th e agc circuitry generated when the ?freeze automatic gai n? command was selected. color killer if ?enable color killer? is selected, the color output is turned off when the running average of the color burst amplitude is below approximately 25% of nominal for four consecutive fields. when the running average of the color burst amplitude is above approximately 25% of nominal for four consecutive fields, the color output is turned on. the color output is also turned off when excessive phase error of the chroma pll is present. if ?force color off? is select ed, color information is never present on the outputs. if ?force color on? is selected, color information is present on the outputs regardless of t he color burst amplitude or chroma pll phase error. y processing the black level is subtracted from the luminance data to remove sync and any blanking pedestal information. negative values of y are supported at this point to allow proper decoding of ?below black? luminance levels. scaling is done to position black at 8-bit code 0 and white at 8-bit code 219. a chroma trap filter may be used to remove any residual color subcarrier from the luminance data. the center frequency of the chroma trap is automatica lly determined from the video standard being decoded. the chroma trap should be disabled during s-video operation to maintain maximum luminance bandwidth. alternately, a 3mhz low-pass filter may be used to HMP8117 8 remove high-frequency y data. this may make a noisy image more pleasing to the user, although softer. coring of the high-frequency y data may be done to reduce low-level high frequency noise. coring of the y data may also be done to reduce low-level noise around black. this forces y data with the following values to a value of 0: coring = 1: 1 coring = 2: 1, 2 coring = 3: 1, 2. 3 high-frequency components of the luminance signal may be ?peaked? to control the sharpness of the image. maximum gain may be selected to occur at either 2.6mhz or the color subcarrier frequency. this may be used to make the displayed image more pleasing to the user. it should not be used if the output video will be compressed, as the circuit introduces high-frequency components that will reduce the compression ratio. the brightness control adds or subtracts a user-specified dc offset to the y data. the cont rast control multiplies the y data by a user-specified amount. these may be used to make the displayed image more pleasing to the user. finally, a value of 16 is added to generate a nominal range of 16 (black) to 235 (white). cbcr processing the cbcr data is low-pass filtered to either 0.85mhz or 1.5mhz. coring of the cbcr data may be done to reduce low-level noise around zero. this forces cbcr data with the following values to a value of 128. coring = 1: 127, 129 coring = 2: 126, 127, 129, 130 coring = 3: 125, 126, 127, 129, 130, 131 the saturation control multiplie s the cbcr data by a user- specified amount. this may be used to make the displayed image more pleasing to the user. the cbcr data may also be optionally multiplied by the contrast value to avoid color shifts when changing contrast. the hue control provides a user-specified phase offset to the color subcarrier during decoding. this may be used to correct slight hue errors due to transmission. ycbcr output format processing y has a nominal range of 16 to 235. cb and cr have a nominal range of 16 to 240, with 128 corresponding to zero. values less than 1 are made 1 and values greater than 254 are made 254. while blank is asserted, y is forced to have a value of 16, with cb and cr forced to have a value of 128, unless vbi data is present. rgb output format processing the 4:2:2 ycbcr data is converted to 4:4:4 ycbcr data and then converted to either 15-b it or 16-bit gamma-corrected rgb (r g b ) data. while blank is asserted, rgb data is forced to a value of 0. 15-bit r g b the following ycbcr to r g b equations are used to maintain the proper black and white levels: r = 0.142(y - 16) + 0.194(cr - 128) g = 0.142(y - 16) - 0.099(cr - 128) - 0.048(cb - 128) b = 0.142(y - 16) + 0.245(cb - 128) the resulting 15-bit r g b data has a range of 0 to 31. values less than 0 are made 0 and values greater than 31 are made 31. the 15-bit r g b data may be converted to 15-bit linear rgb, using the following equations. although the pal specifications specify a gamma of 2.8, a gamma of 2.2 is normally used. the HMP8117 al lows the selection of the gamma to be either 2.2 or 2. 8, independent of the video standard. for gamma = 2.2: for r g b < 0.0812*31 r = (31)((r /31)/4.5) g = (31)((g /31)/4.5) b = (31)((b /31)/4.5) for r g b >= 0.0812*31 r = (31)(((r /31) + 0.099)/1.099) 2.2 g = (31)(((g /31) + 0.099)/1.099) 2.2 b = (31)(((b /31) + 0.099)/1.099) 2.2 for gamma = 2.8: r = (31)(r /31) 2.8 g = (31)(g /31) 2.8 b = (31)(b /31) 2.8 16-bit r g b the following ycbcr to r g b equations are used to maintain the proper black and white levels: r = 0.142(y - 16) + 0.194(cr - 128) g = 0.288(y - 16) - 0.201(cr - 128) - 0.097(cb - 128) b = 0.142(y - 16) + 0.245(cb - 128) the resulting 16-bit r g b data has a range of 0 to 31 for r and b , and a range of 0 to 63 for g . values less than 0 are made 0; r and b values greater than 31 are made 31, g values greater than 63 are made 63. the 16-bit r g b data may be converted to 16-bit linear rgb, using the following equations. alt hough the pal specifications specify a gamma of 2.8, a gamma of 2.2 is normally used. the HMP8117 allows the selection of the gamma to be either 2.2 or 2.8, independent of the video standard. HMP8117 9 for gamma = 2.2: for r b < 0.0812*31, g < 0.0812*63 r = (31)((r /31)/4.5) g = (63)((g /63)/4.5) b = (31)((b /31)/4.5) for r b >= 0.0812*31, g >= 0.0812*63 r = (31)(((r /31) + 0.099)/1.099) 2.2 g = (63)(((g /63) + 0.099)/1.099) 2.2 b = (31)(((b /31) + 0.099)/1.099) 2.2 for gamma = 2.8: r = (31)(r /31) 2.8 g = (63)(g /63) 2.8 b = (31)(b /31) 2.8 built-in video generation the decoder can be configured to output a full-screen of built-in blue, black or 75% color bar patterns. the type of pattern generated is determined by bits 2-1 of the output format register 02 h . when built-in video generation is not desired, the bits need to be set for normal operation to pass decoded video. if the decoder is currently locked to a video source on the input, the output data timing will be based on the input video source. if an input video source is not detected, internally- generated output data timing will be used. the following table lists the data codes output for each built-in video pattern in ycbcr format. pixel port timing the the timing and format of the output data and control signals is presented in the following sections. refer to the section ?cycle slipping and real-time pixel jitter? for pll and interface considerations. hsync and vsync timing the hsync and vsync output timing is vmi v1.4 compatible. figures 3-6 illustrate the video timing. the leading edge of hsync is synchronous to the video input signal and has a fixed latency due to internal pipeline processing. the pulse width of the hsync is defined by the end hsync register 36 h , where the trailing edge of hsync has a programmable delay of 0-510 clk2 cycles from the leading edge. the leading edge of vsync is asserted approximately half way through the first serration pulse of each field. an accumulator is used to detect a low-time period within the serration pulse. since the leading edge of vsync is detected, it should not be used for timing with respect to hsync or blank . the trailing edge of vsync implements the vmi handshake with hsync in order to determine field information without using the field pin. for an odd field, the trailing edge of vsync is 5 1 clk2 cycles after the trailing edge of the hsync that follows the last equalization pulse. refer to figures 3 and 5. for an even field, the tra iling edge of vsync is 5 1 clk2 cycles after the leading edge of the hsync that follows the last equalization pulse. refer to figures 4 and 6. field timing when field information can be determined from the input video source, the field output pin reflects the video source field state. when field information cannot be determined from the input video source, th e field output pi n alternates its state at the beginning of ea ch field. field changes state 5 1 clk2 cycles before the leading edge of vsync . table 2. built-in video pattern data codes pattern: color y cb cr 75% color bar: white yellow cyan green magenta red blue black b4 h a2 h 83 h 70 h 54 h 41 h 23 h 10 h 80 h 2c h 9c h 48 h b8 h 64 h d4 h 80 h 80 h 8e h 2c h 3a h c6 h d4 h 72 h 80 h blue screen: blue 4b h d9 h 88 h black screen: black 10 h 80 h 80 h video vsync field ?even? field figure 3. ntsc(m) and pal(m) odd field timing ?odd? field hsync input 523 5245251234567 522 521 12345678910 525 524 pal(m) line# ntsc(m) line# HMP8117 10 blank and dvalid timing dvalid is asserted when p15-p0 contain valid data. the behavior of the dvalid output is determined by bit 4 (dvld_ltc) and bit 5 (dlvd_dcyc) of the genlock control register 04 h for each video output mode. the blank output pin is used to distinguish the blanking interval period from active video data. the blanking intervals are programmable in both horizontal and vertical dimensions. reference figure 7 for active video timing and use table 3 for typical blanking programming values. during active scan lines, blank is asserted when the horizontal pixel count matches the value in the start h_blank register 31 h /30 h . the pixel counter is 000 h at the leading edge of the sync tip after a fixed pipeline delay. since blanking normally occurs on the front porch, (prior to count 000h) the start h_blank count must be programmed with a large value from the previous line. refer to the last pixel count from table 3. blank is negated when the horizontal pixel count matches the value in the end h_blank register 32 h . note that horizontally, blank is programmable with two pixel resolution. start v_blank register 34 h /33 h and end v_blank register 35 h determine which scan lines are blanked for each field. during inactive scan lines, blank is asserted during the entire scan line. half-line blanking of the output video cannot be done. figure 4. ntsc(m) and pal(m) even field timing video vsync field ?odd? field ?even? field hsync input 261 pal(m) line# 262 263 264 265 266 267 268 269 270 260 259 264 ntsc(m) line# 265 266 267 268 269 270 271 272 273 263 262 video vsync field ?even? field figure 5. pal(b, d, g, h, i, n, n c ) odd field timing ?odd? field hsync input 623 line # 6246251234567 622 621 figure 6. pal(b, d, g, h, i, n, n c ) even field timing video vsync field ?odd? field ?even? field hsync input 311 line # 312 313 314 315 316 317 318 319 320 310 309 HMP8117 11 table 3. typical values for h_blank and v_blank registers video standard (msb/lsb) active pixels/ line total pixels/ line last pixel count start h_blank (31h/30h) end h_blank (32h) start v_blank (34h/33h) end v_blank (35h) rectangular pixels ntsc (m), pal (m) pal (b, d, g, h, i, n, n c ) 720 720 858 864 857 (0359 h ) 863 (035f h ) 842 (034a h ) 852 (0354 h ) 122 (7a h ) 132 (84 h ) 259 (0103 h ) 310 (0136 h ) 19 (13 h ) 22 (16 h ) square pixels ntsc (m), pal (m) pal (b, d, g, h, i, n, n c ) 640 768 780 944 779 (030b h ) 943 (03af h ) 758 (02f6 h ) 922 (039a h ) 118 (76 h ) 154 (9a h ) 259 (0103 h ) 310 (0136 h ) 19 (13 h ) 22 (16 h ) note: 3. the line numbering for pal (m) is the ntsc (m) line count minus 3 per the video standards. figure 7. typical active video regions lines 1 - 22 not active ntsc m pal b, d, g, h, i, n, n c odd field lines 263 - 284 not active even field lines 1 - 22 not active lines 311 - 335 not active 858 number of pixels total pixels active pixels 720 (780) (640) 864 total pixels active pixels 720 (944) (768) rectangular (square) sync and back porch front porch vertical blanking ntsc pal 480 active lines/frame (ntsc, pal m) 576 active lines/frame (pal) (lines 23-262) 240 active lines per field (lines 285 - 524) 240 active lines per field line 525 not active (lines 23 - 310) 288 active lines per field lines 624-625 not active (lines 336 - 623) 288 active lines per field table 4. pixel output formats pin name 8-bit, 4:2:2, ycbcr 16-bit, 4:2:2, ycbcr 15-bit, rgb, (5,5,5) 16-bit, rgb, (5,6,5) bt.656 p0 p1 p2 p3 p4 p5 p6 p7 0 [0] 0 [0] 0 [0] 0 [0] 0 [0] 0 [0] 0 [0] 0 [0] cb0, cr0 [d0 n+1 ] cb1, cr1 [d1 n+1 ] cb2, cr2 [d2 n+1 ] cb3, cr3 [d3 n+1 ] cb4, cr4 [d4 n+1 ] cb5, cr5 [d5 n+1 ] cb6, cr6 [d6 n+1 ] cb7, cr7 [d7 n+1 ] b0 [d0 n+1 ] b1 [d1 n+1 ] b2 [d2 n+1 ] b3 [d3 n+1 ] b4 [d4 n+1 ] g0 [d5 n+1 ] g1 [d6 n+1 ] g2 [d7 n+1 ] b0 [d0 n+1 ] b1 [d1 n+1 ] b2 [d2 n+1 ] b3 [d3 n+1 ] b4 [d4 n+1 ] g0 [d5 n+1 ] g1 [d6 n+1 ] g2 [d7 n+1 ] 0 [0] 0 [0] 0 [0] 0 [0] 0 [0] 0 [0] 0 [0] 0 [0] p8 p9 p10 p11 p12 p13 p14 p15 y0, cb0, cr0 [d0] y1, cb1, cr1 [d1] y2, cb2, cr2 [d2] y3, cb3, cr3 [d3] y4, cb4, cr4 [d4] y5, cb5, cr5 [d5] y6, cb6, cr6 [d6] y7, cb7, cr7 [d7] y0 [d0 n ] y1 [d1 n ] y2 [d2 n ] y3 [d3 n ] y4 [d4 n ] y5 [d5 n ] y6 [d6 n ] y7 [d7 n ] g3 [d0 n ] g4 [d1 n ] r0 [d2 n ] r1 [d3 n ] r2 [d4 n ] r3 [d5 n ] r4 [d6 n ] 0 [d7 n ] g3 [d0 n ] g4 [d1 n ] g5 [d2 n ] r0 [d3 n ] r1 [d4 n ] r2 [d5 n ] r3 [d6 n ] r4 [d7 n ] ycbcr data, ancillary data, sav and eav sequences [d0 - d7, where p8 corresponds to d0] note: 4. definitions in brackets are port definitions during raw vbi dat a transfers. refer to the section on teletext for more informa tion on raw vbi. HMP8117 12 pixel output port pixel data is output via the p0-p15 pins. refer to table 4 for the output pin definition as a function of the output mode. refer to the section ?cycle slipping and real-time pixel jitter? for pll and interface considerations. 8-bit ycbcr output each ycbcr data byte is outp ut following each rising edge of clk2. the ycbcr data is multiplexed as [cb y cr y cb y cr y ...], with the first active da ta each scan line containing cb data. the pixel output timing is shown in figures 8 and 9. blank , hsync , vsync , dvalid , vbivalid , and field are output following the rising edge of clk2. when blank is asserted and vbivalid is deasserted, the ycbcr outputs have a value of 16 for y and 128 for cb and cr. the behavior of the dvalid output is determined by bit 4 (dvld_ltc) of the genlock control register 04 h . 16-bit ycbcr, 15-bit rgb, or 16-rgb output for 16-bit ycbcr, 15-bit rg b data, or 16-bit rgb output modes, the data is output following the rising edge of clk2 with dvalid asserted. either linea r or gamma-corrected rgb data may be output. the pixel output timing is shown in figures 10 to 13. blank , hsync , vsync , dvalid , vbivalid , and field are output following the rising edge of clk2. when blank is asserted and vbivalid is deasserted, the ycbcr outputs have a value of 16 for y and 128 for cb and cr; the rgb outputs have a value of 0. the behavior of the dvalid output is determined by bit 4 (dvld_ltc) and bit 5 (dlvd_dcyc) of the genlock control register 04 h . note: 5. y 0 is the first active luminance pixel data of a line. cb 0 and cr 0 are first active chrominance pixel data in a line. cb and cr will alternate every cycle due to the 4:2:2 subsampling. pixe l data is not output during the blanking period, but the values are forced to blanking levels. figure 8. output timing for 8-bit ycbcr mode (dvld_ltc = 0) clk dvalid p[15-8] t dvld cb 0 y 0 cr 0 cb 2 y 2 cr 2 y 1 y 3 cb 4 y 4 blank clk dvalid p[15-8] t dvld cb 0 y 0 cr 0 cb 2 y 2 cr 2 y 1 y 3 cb 4 n otes: 6. y 0 is the first active luminanc e pixel data of a line. cb 0 and cr 0 are first active chrominance pixel data in a line. cb and cr will alternate every cycle due to the 4:2:2 subsampling. pixel data is not output dur ing the blanking period, but the values are forced to blanking levels. 7. when dvld_ltc is set to 1, the polarity of dvalid needs to be set to active low, otherwise dvalid will stay low during active video and be gated with the clock only during the blanking interval. figure 9. output timing for 8-bit ycbcr mode (dvld_ltc = 1) y 4 blank HMP8117 13 notes: 8. y 0 is the first active luminance pixel data of a line. cb 0 and cr 0 are first active chrominance pixel data in a line. cb and cr will alternate every cycle due to the 4:2:2 subsampling. 9. blank is asserted per figure 7. figure 10. output timing for 16-bit ycbc r mode (dvld_ltc = 0, dvld_dcyc = 0) y 0 cb0 clk dvalid blank p15-p8 p7-p0 t dvld y 1 y 2 y 3 y 4 cr0 cb2 cr2 cb4 note: 10. blank is asserted per figure 7. figure 11. output timing for 16-bit [15-bit] rgb mode (dvld_ltc = 0, dvld_dcyc = 0) r 0 g0 clk dvalid p15-p11 p10-p5 t dvld r 1 r 2 r 3 r 4 g1 g2 g3 g4 b0 p4-p0 b1 b2 b3 b4 [p9-p5] [p14-p10] HMP8117 14 8-bit bt.656 output for the bt.656 output mode, data is output following each rising edge of clk2. the bt.656 eav and sav formats are shown in table 5 and the pixel output timing is shown in figure 14. the eav and sav timing is determined by the programmed horizontal and vertical blank timing. blank , hsync , vsync , dvalid , vbivalid , and field are output following the rising edge of clk2. during the blanking intervals, the ycbcr outputs have a value of 16 for y and 128 for cb and cr, unless ancillary data is present. notes: 11. y 0 is the first active luminance pixel of a line. cb 0 and cr 0 are first active chrominance pixels in a li ne. cb and cr will alternate every cycle due to the 4:2:2 subsampling. 12. blank is asserted per figure 7. 13. dvalid is asserted for every valid pixel during both active and blanking regions. figure 12. output timing for 16-bit ycbc r mode (dvld_ltc = 0, dvld_dcyc = 1) y 0 cb 0 y 1 cr 0 y 2 cb 2 y 3 cr 2 y 4 cb 4 clk dvalid p15-p8 p7-p0 t dvld notes: 14. blank is asserted per figure 7. 15. davlid is asserted for every valid pixel duri ng both active and blanking regions. dvalid is not a 50% duty cycl e synchronous output and will appear to jitter as the output sample rate converter adjusts the output timing for various data rates and clock frequency input s. figure 13. output timing for 16-bit [15-bit] rgb mode (dvld_ltc = 0, dvld_dcyc = 1) r0 g 0 r 1 g 0 r 2 g 2 r 3 g 2 r 4 g 4 clk dvalid blank t dvld b 0 b 1 b 2 b 3 b 4 p15-p11 p10-p5 p4-p0 [p9-p5] [p14-p10] HMP8117 15 . advanced features in addition to digitizing an analog video signal the HMP8117 has hardware to process different types of vertical blanking interval (vbi) data as described in the following sections. ?sliced? vbi data capture the HMP8117 implements ?slic ed? data capture of select types of vbi data. the vbi decoders incorporate detection hysteresis to prevent them from rapidly turning on and off due to noise and transmission errors. in order to handle real- world signals, the vbi decoders also compensate for dc offsets and amplitude variations. closed captioning during closed captioning captur e, the scan lines containing captioning information are monitored. if closed captioning is enabled and captioning data is present, the c aption data is loaded into the caption data registers. detection of closed captioning the closed caption decoder monitors the appropriate scan lines looking for the clock run-in and start bits used by captioning. if found, it locks to the cl ock run-in, the caption data is sampled and loaded into shift registers, and the data is then transferred to the caption data registers. if the clock run-in and start bits are not found, it is assumed the scan line contains video data unless other vbi information is detected , such as teletext. once the clock run-in and start bits are found on the appropriate scan line for four consecutive odd fields, the closed captioning odd field detect status bit is set to ?1?. it is reset to ?0? when the clock run-in and start bits are not found on the appropriate scan lines for four consecutive odd fields. once the clock run-in and start bits are found on the appropriate scan line for four consecutive even fields, the closed captioning even field detect status bit is set to ?1?. it is reset to ?0? when the clock run-in and start bits are not found on the appropriate scan lines for four consecutive even fields. reading the caption data the caption data registers may be accessed in two ways: via the i 2 c interface or as bt.656 ancillary data. clk dvalid blank p[15-8] t dvld ff 00 00 cb 0 y 0 cr 0 status y 1 cb 2 notes: 16. y 0 is the first active luminance pixel data of a line. cb 0 and cr 0 are first active chrominance pixel data in a line. cb and cr will alternate every cycle due to the 4:2:2 s ubsampling. pixel data is not output during the blanking period. 17. notice that dvalid is not asserted during the preamble and that blank is still asserted. 18. see table 5 for status bit definitions. figure 14. output timing for 8-bit bt.656 mode y 2 table 5. bt.656 eav and sav sequences pixel input p15 p14 p13 p12 p11 p10 p9 p8 preamble 11111111 00000000 00000000 status word 1 f v h p3 p2 p1 p0 notes: 19. p3 = v xor h; p2 = f xor h; p1 = f xor v; p0 = f xor v xor h 20. f: ?0? = field 1; ?1? = field 2 21. v: ?1? during vertical blanking 22. h: ?0? at sav (start of active vi deo); ?1? at eav (end of active video) HMP8117 16 captioning disabled on both lines in this case, any caption data present is ignored. the caption odd field read status bit and the caption even field read status bit are always a ?0?. odd field captioning in this case, any caption data present on line 284 (or line 281 or 335 in the pal modes) is ignored. caption data present on line 21 (or line 18 or 22 in the pal modes) is captured into a shift register then transferred to closed caption_odd_a register 20 h and closed caption_odd_b register 21 h . the caption even field read status bit is always a ?0?. the caption odd field read status bit is set to ?1? after data has been transferred from the shift register to the closed caption_odd_a and closed caption_odd_b registers. it is set to ?0? after the data has been read out. even field captioning in this case, any caption data present on line 21 (or line 18 or 22 in the pal modes) is ignored. caption data present on line 284 (or line 281 or 335 in the pal modes) is captured into a shift register then transferred to closed caption_even_a register 22 h and closed caption_even_b register 23 h . the caption odd field read status bit is always a ?0?. the caption even field read status bit is set to ?1? after data has been transferred from the shift register to the closed caption_even_a and cl osed caption_even_b registers. it is set to ?0? after the data has been read out. odd and even field captioning caption data present on line 21 (or line 18 or 22 in the pal modes) is captured into a shif t register then transferred to the closed caption_odd_a and closed caption_odd_b registers. ca ption data present on line 284 (or line 281 or 335 in the pal modes) is captured into a shift register then tr ansferred to the closed caption_even_a and cl osed caption_even_b registers. the caption odd field read status bit is set to ?1? after data has been transferred from the shift register to the closed caption_odd_a and closed caption_odd_b registers. it is set to ?0? afte r the data has been read out. the caption even field read status bit is set to ?1? after data has been transferred from the shift register to the closed caption_even_a and cl osed caption_even_b registers. it is set to ?0? after the data has been read out. widescreen si gnalling (wss) during wss capture (itu-r bt.1119 and eiaj cpx-1204), the scan lines containing wss information are monitored. if wss is enabled and wss data is present, the wss data is loaded into the wss data registers. detection of wss the wss decoder monitors the appropriate scan lines looking for the run-in and start codes used by wss. if found, it locks to the run-in code, the wss data is sampled and loaded into shift registers, and the data is then transferred to the wss data registers. if the run-in and start codes ar e not found, it is assumed the scan line contains video data unless other vbi information is detected, such as teletext. once the run-in and start code s are found on the appropriate scan line for four consecutive odd fields, the wss line 20 detect status bit is se t to ?1?. it is reset to ?0? when the run-in and start codes are not found on the appropriate scan lines for four consecutive odd fields. once the run-in and start code s are found on the appropriate scan line for four consecutive even fields, the wss line 283 detect status bit is set to ?1?. it is reset to ?0? when the clock run-in and start bits are not found on the appropriate scan lines for four consecutive even fields. reading the wss data the wss data registers may be accessed in two ways: via the i 2 c interface or as bt.656 ancillary data. wss disabled on both lines in this case, any wss data present is ignored. the wss odd field read status bit and the wss even field read status bit are always a ?0?. odd field wss in this case, any wss data present on line 283 (or line 280 or 336 in the pal modes) is ignored. wss data present on line 20 (or line 17 or 23 in the pal modes) is captured into a shift register then transferred to the wss_odd_a and wss_odd_b data registers. the wss even field read status bit is always a ?0?. the wss odd field read status bit is set to ?1? after data has been transferred from the shift register to the wss_odd_a and wss_odd_b registers. it is set to ?0? after the data has been read out. even field wss in this case, any wss data present on line 20 (or line 17 or 23 in the pal modes) is ignored. wss data present on line 283 (or line 280 or 336 in the pal modes) is captured into a shift register then transf erred to the wss_even_a and wss_even_b data registers. the wss odd field read status bit is always a ?0?. the wss even field read status bit is set to ?1? after data has been transferred from the shift re gister to the wss_even_a and wss_even_b registers. it is set to ?0? after the data has been read out. HMP8117 17 odd and even wss wss data present on line 20 (or line 17 or 23 in the pal modes) is captured into a shif t register then transferred to the wss_odd_a and wss_odd_b registers. wss data present on line 283 (or line 280 or 336 in the pal modes) is captured into a shift regist er then transferred to the wss_even_a and wss_even_b registers. the wss odd field read status bit is set to ?1? after data has been transferred from the shift register to the wss_odd_a and wss_odd_b registers. it is set to ?0? after the data has been read out. the wss even field read status bit is set to ?1? after data has been transferred from the shift register to the wss_even_a and wss_even_b registers. it is set to ?0? after the data has been read out. bt.656 ancillary data through the bt.656 interface the HMP8117 can generate non-active video data which contains cc, wss, teletext or real-time control interface (rtci) information. teletext and rtci data is only available as bt.656 ancillary data. vbivalid output timing the vbivalid output is asserted w hen outputting closed captioning, wide screen signalling, teletext or rtci data as bt.656 ancillary data. it is asserted during the entire bt.656 ancillary data packet time, including the preamble. bt.656 closed captioning and wide screen signalling table 6 illustrates the format when outputting the caption data registers as bt.656 ancill ary data. the ancillary data is present during the horizontal bl anking interval after the line containing the captioning information. table 7 illustrates the format when outputting the wss data registers as bt.656 ancillary data. the ancillary data is present during the horizontal bl anking interval after the line containing the wss information. clk vbivalid p[15-8] t dvld 00 ff ff blk # # bytes/4 byte #1 data id notes: 23. bt.656 vbi ancillary starts with a 00h , ffh and ffh sequence which is opposite to the sav/eav sequence of ffh, 00h and 00h. 24. during active vbi data intervals, dvalid is deasserted and blank is asserted. figure 15. output timing for bt.656 vbi data transfers (cc, wss, teletext, rtci) byte #2 byte #3 byte #4 table 6. reading the closed caption data as bt.656 ancillary data pixel output p15 p14 p13 p12 p11 p10 p9 p8 preamble 0000000 0 1111111 1 1111111 1 data id p14 ep110000 = odd field data 1 = even field data data block number p14 ep00000 1 data word count p14 ep00000 1 caption data p14 ep 0 0 bit 15 bit 14 bit 13 bit 12 p14 ep 0 0 bit 11 bit 10 bit 9 bit 8 p14 ep 0 0 bit 7 bit 6 bit 5 bit 4 p14 ep 0 0 bit 3 bit 2 bit 1 bit 0 crc p14 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes: 25. ep = even parity for p8-p13. 26. crc = sum of p8-p14 of data id through last user data word. preset to all zeros, carry is ignored. HMP8117 18 teletext the HMP8117 supports itu-r bt.653 625-line and 525-line teletext system b, c and d ca pture. nabts (north american broadcast teletext specificati on) is the same as bt.653 525-line system c, which is al so used to tr ansmit intel intercast? information. wst (world system teletext) is the same as bt.653 system b. figure 16 shows the basic structure of a video signal that contains teletext data. the scan lines containing teletext information are monitored. if teletext is enabled and teletext data is present, the teletext data is output as bt.656 ancillary data. detection of teletext the teletext decoder monitors the scan lines, looking for the 16-bit clock run-in (sometimes referred to as the clock synchronization code) used by te letext. if found, it locks to the clock run-in, the teletext data is sampled and loaded into shift registers, and the data is then transferred to internal holding registers. if the clock run-in is not found, it is assumed the scan line contains video data unless other vbi information is detected, such as wss. if a teletext clock run-in is found before line 23 or line 289 for ntsc and (m) pal, or line 336 for (b, d, g, h, i, n, n c ) pal, the vbi teletext detect status bit is immediately set to ?1?. if not found by these lines, the status bit is immediately reset to ?0?. accessing the teletext data the teletext data must be outpu t as bt.656 ancillary data. the i 2 c interface does not have the bandwidth to output teletext information when needed. table 8 illustrates the teletext bt.656 ancillary data format and figure 15 depicts the portion of the incoming teletext signal which is sliced and output as part of the ancillary data stream. the teletext data is present during the horizontal blanking interval after the li ne containing the teletext information. the actual bt.656 bytes that contain teletext data only contain 4 bits of the actual data packet. note that only the data packet of figure 16 is sent as ancillary data; the clock run-in is not included in the data stream. table 7. outputting the sliced wss data as bt.656 ancillary data pixel output p15 p14 p13 p12 p11 p10 p9 p8 preamble 0000000 0 1111111 1 1111111 1 data id p14 ep11001 0 = odd field data 1 = even field data data block number p14 ep00000 1 data word count p14 ep00001 0 wss data p14 ep0000bit 13 bit 12 p14 ep 0 0 bit 11 bit 10 bit 9 bit 8 p14 ep 0 0 bit 7 bit 6 bit 5 bit 4 p14 ep 0 0 bit 3 bit 2 bit 1 bit 0 wss crc data p14 ep0000bit 5 bit 4 p14 ep 0 0 bit 3 bit 2 bit 1 bit 0 p14 ep00000 0 p14 ep00000 0 crc p14 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes: 27. ep = even parity for p8-p13. 28. wss crc data = ?00 0000? during pal operation. 29. crc = sum of p8-p14 of data id through last user data word. preset to all zeros, carry is ignored. HMP8117 19 ?raw? vbi data capture ?raw? data capture of vbi dat a during blanked scan lines may be optionally implemented. in this instance, the active line time of blanked scan lines are sampled at the clk2 rate, and output onto the pixel outputs. this permits software decoding of the vbi data to be done. the line mask registers specify on which scan lines to generate ?raw? vbi data. if the raw vbi all bit is enabled, all the video lines are treated as raw vbi data, excluding the equalization and serration lines. the start and end timing of capturing ?raw? vbi data on a scan line is determined by the start and end raw vbi registers. this allows the prop er capture of ?raw? vbi data regardless of the blank# output timing for active video. the blanking level is subtra cted from the ?raw? vbi data samples, and the result is output onto the pixel outputs. note both ?sliced? and ?raw? vbi data may be available on the same line. during ntsc operation, the first possible line of vbi data is lines 10 and 272, and the last possible lines are the last blanked scan lines. lines 1-9 and 264-271 are always blanked. during pal (b, d, g, h, i, n, n c ) operation, the first possible line of vbi data are lines 6 and 318, and the last possible lines are the last blanked scan lines. lines 623-5 and 311- 317 are always blanked. notes: 30. the msb is bit number: 271 for system c, 279 for system b 525-line and 343 for system b 625-line. 31. the clock run-in is 16 bits wide for both systems and is not included in the bt.656 ancillary data stream. 32. the bit rate is 5.727272 mbits/s for system b and c on 525/ 60 systems and 6.9375 and 5.734375 mbits/second respectively for 625/50 systems. 33. teletext vbi video signal figure 16. teletext vbi video signal data packet clock run-in bit 0 msb table 8. outputting the sliced teletext data as bt.656 ancillary data pixel input p15 p14 p13 p12 p11 p10 p9 p8 preamble 0 0 0 0 0 0 0 0 1 1 1 1 1111 1 1 1 1 1111 data id p14 ep 1 1 0100 data block number p14 ep 0 0 0001 data word count p14 ep 0 1 0110 teletext data (b, 625-line = 43 bytes) (b, 525-line = 35 bytes) (c = 34 bytes) p14 ep 0 = 525-line 1 = 625-line 0 = system b 1 = system c bit 343 bit 342 bit 341 bit 340 p14 ep 0 0 bit 339 bit 338 bit 337 bit 336 : p14 ep 0 0 bit 7 bit 6 bit 5 bit 4 p14 ep 0 0 bit 3 bit 2 bit 1 bit 0 reserved p14 ep 0 0 0000 p14 ep 0 0 0000 crc p14 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes: 34. ep = even parity for p8-p13. 35. crc = sum of p8-p14 of data id through last user data word. preset to all zeros, carry is ignored. 36. for 525-line system b, bits 280-343 are ?0?. 37. for system c, bits 272-343 are ?0?. HMP8117 20 during pal (m) operation, the first possible line of vbi data is lines 7 and 269, and the last possible lines are the last blanked scan lines. lines 523-6 and 261-268 are always blanked. real time control interface the real time control interface (rtci) outputs timing information for a ntsc/pal encoder as bt.656 ancillary data. this allows the encoder to generate ?clean? output video. rtci information via bt.656 ancillary data is shown in table 9. if enabled, this transfer occurs once per line and is completed before the start of the sav sequence. the psw bit is always a ?0? for ntsc encoding. during pal encoding, it indicates the sign of v (?0? = negative; ?1? = positive) for that scan line. host interface all internal registers may be written to or read by the host processor at any time, except for those bits identified as read-only. the bit descriptions for the control registers are listed beginning with table 10. the HMP8117 supports the fa st-mode (up to 400kbps) i 2 c interface consisting of the sda and scl pins. the device acts as a slave for receiving and transmitting data over the serial interface. when the interface is not active, scl and sda must be pulled high using external 4k ? pull-up resistors. the sa input pin determines the slave address for the HMP8117. if the sa pin is pulled low, the address is 1000100x b . if the sa pin is pulled high through a 10k ? pull- up resistor, the address is 1000101x b . (this ?x? bit in the address is the i 2 c read flag.) data is placed on the sda line when the scl line is low and held stable when the scl line is pulled high. changing the state of the sda line while scl is high will be interpreted as either an i 2 c bus start or stop condition as indicated by figure 18. during i 2 c write cycles, the first data byte after the slave address is treated as the control register sub address and is written into the internal address register. any remaining data bytes sent during an i 2 c write cycle are written to the control registers, beginning with the re gister specified by the address register as given in the first byte. the address register is then auto-incremented after each additional data byte sent on the i 2 c bus during a write cycle. writes to reserved bits within register s or reserved registers are ignored. in order to perform a read from a specific control register within the HMP8117, an i 2 c bus write must first be performed to properly setup the address register. then an i 2 c bus read can be performed to read from the desired control register(s). as a result of needing the write cycle for a read cycle there are actually two start conditions as shown in figure 19. the address register is then auto- incremented after each byte read during the i 2 c read cycle. reserved registers return a value of 00 h . table 9. outputting rtci as bt.656 ancillary data pixel input p15 p14 p13 p12 p11 p10 p9 p8 preamble 0 0000000 1 1111111 1 1111111 data id p14 ep110101 data block number p14 ep000001 data word count p14 ep000011 hpll increment p14 ep000000 p14 ep000000 p14 ep000000 p14 ep000000 fscpll increment p14 ep psw 0 bit 31 bit 30 bit 29 bit 28 p14 ep f2 = 0 f1 = 0 bit 27 bit 26 bit 25 bit 24 : p14 ep 0 0 bit 7 bit 6 bit 5 bit 4 p14 ep 0 0 bit 3 bit 2 bit 1 bit 0 crc p14 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes: 38. ep = even parity for p8-p13. 39. crc = sum of p8-p14 of data id through last user data word. preset to all zeros, carry is ignored. HMP8117 21 figure 17. i 2 c timing diagram sda scl t buf t low t high t r t f t su:data t hd:data tsu:stop sda scl start condition s 1-7 address 8 r/w 9 ack 1-7 data 89 ack stop condition p figure 18. i 2 c serial data flow s = start cycle p = stop cycle a = acknowledge from master from HMP8117 0x88 data write data data 0x88 data read na = no acknowledge 0x89 1000 1000 (r/w) 1000 1000 figure 19. registe r write/read flow s chip addr a sub addr data data p na chip addr s sub addr chip addr s p a a a a a a register pointed to by sub addr optional frame may be repeated n times a register pointed to by sub addr optional frame may be repeated n times HMP8117 22 control registers r table 10. control register summary sub- address control register reset/ default value use value comments 00 h product id 16 h or 17 h returns last two digits of part number in hex format. 01 h input format 19 h defaults to auto-detect of input video standard. 02 h output format 00 h defaults to 16-bit ycbcr data format. 03 h output control 00 h c0 h set bits 7-6 to enable data and timing outputs. 04 h genlock control 09 h defaults to 27mhz clk2, rectangular pixel mode 05 h analog input control 10 h defaults to input signal select = cvbs1. 06 h color processing 52 h 08 h luma processing 04 h 0a h sliced vbi data enable 00 h 0b h sliced vbi data output 00 h 0c h vbi data status 00 h 0e h video status 00 h 0f h interrupt mask 00 h 10 h interrupt status 00 h 11 h raw vbi control 00 h 12 h raw vbi start count 7a h 14 h /13 h raw vbi stop count msb/lsb 03 h /4a h 15 h raw vbi line mask_7_0 fe h 16 h raw vbi line mask_15_8 1f h 17 h raw vbi line mask_18_16 00 h 18 h brightness 00 h 19 h contrast 80 h 1a h hue 00 h 1b h saturation 80 h 1c h color gain adjust 40 h 1d h video gain adjust 80 h 1e h sharpness 10 h 1f h host control 00 h set bit 7 for soft reset. set bit 6 for power down. 20 h -23 h closed caption data registers 80 h 24 h -29 h wss data & crc registers 00 h 31 h /30 h start h_blank msb/lsb 03 h /4a h table 3 blank programming changes for each video standard. 32 h end h_blank 7a h table 3 (same as above) 34 h /33 h start v_blank msb/lsb 01 h /02 h table 3 (same as above) 35 h end v_blank 12 h table 3 (same as above) 36 h end hsync 30 h table 3 (same as above) 37 h hsync detect window 20 h 90 h a wider window tolerates poorly timed video sources. 41 h mv control 26 h 42 h reserved 00 h 30 h set bits 5-4 to 11 b for optimum performance. 50 h programmable fractional gain 0c h 21 h a slower pfg improv es agc stability. 51 h mv stripe gate 14 h 52 h reserved 02 h 22 h set bit 5 to ?1? for optimum performance. 53 h agc hysteresis 00 h f0 h larger hysteresis impr oves agc stability. 7f h device revision 01 h production baseline revision is 01 h . sub-addresses: 40 h , 43 h -4f h are reserved. reads from these r egisters may return non-zero values. sub-addresses: 07 h , 09 h , 0d h , 2a h -2f h , 38 h -3f h and 54 h -7e h are unused. reads from these registers return 00 h . writes are ignored. HMP8117 23 table 11. product id register sub address = 00 h bit number function description reset state 7-0 product id this 8-bit register specifies the last two digits of the product number. data written to this read- only register is ignored. 17 h table 12. input format register. sub address = 01 h bit number function description reset state 7 reserved 0 b 6-5 video timing standard these bits are read only unless bit 4 = ?0?. 00 = (m) ntsc 01 = (b, d, g, h, i, n) pal 10 = (m) pal 11 = combination (n) pal; also called (n c ) pal 00 b 4 auto detect video standard 0 = manual selection of video timing standard 1 = auto detect of video timing standard 1 b 3 setup select typically, this bit should be a ?1? during (m) ntsc and (m, n) pal operation. otherwise, it should be a ?0?. 0 = video source has a 0 ire blanking pedestal 1 = video source has a 7.5 ire blanking pedestal 1 b 2-1 reserved 00 b 0 adaptive sync slice enable this bit specifies whether to use fixed or adaptive sync slicing. adaptive sync slicing automatically determines the midpoint of the sync amplitude to determine timing. 0 = fixed sync slicing 1 = adaptive sync slicing 1 b table 13. output format register. sub address = 02 h bit number function description reset state 7-5 output color format 000 = 16-bit 4:2:2 ycbcr100 = 16-bit rgb 001 = 8-bit 4:2:2 ycbcr101 = reserved 010 = 8-bit parallel bt.656110 = reserved 011 = 15-bit rgb111 = reserved 000 b 4-3 rgb gamma select these bits are ignored exc ept during rgb output modes. 00 = linear rgb (gamma of input source = 2.2) 01 = linear rgb (gamma of input source = 2.8) 10 = gamma-corrected rgb (gamma = gamma of input source) 11 = reserved 00 b 2-1 output color select 00 = normal operation10 = output black field 01 = output blue field11 = output 75% color bars 00 b 0 reserved set to ?0? for proper operation. vert ical pixel siting control is not supported. 0 b HMP8117 24 table 14. output control register. sub address = 03 h bit number function description reset state 7 video data output enable this bit is used to enable the p0-p15 outputs. 0 = outputs 3-stated. 1 = outputs enabled 0 b 6 video timing output enable this bit is used to enable the hsync , vsync , blank , field, vbivalid , dvalid , and intreq outputs. 0 = outputs 3-stated. 1 = outputs enabled 0 b 5 field polarity 0 = active low (low during odd fields). 1 = active hi gh (high during odd fields) 0 b 4blank polarity 0 = active low (low during blanki ng). 1 = active high (high during blanking) 0 b 3 hsync polarity 0 = active low (low during horizontal sy nc). 1 = active high (high during horizontal sync) 0 b 2 vsync polarity 0 = active low (low during vertical sy nc). 1 = active high (hi gh during vertical sync) 0 b 1 dvalid polarity 0 = active low (low dur ing valid pixel data). 1 = active high (high during valid pixel data) 0 b 0 vbivalid polarity 0 = active low (low during vbi data ). 1 = active high (high during vbi data) 0 b table 15. genlock control register sub address = 04 h bit no. function description reset state 7 aspect ratio mode 0 = rectangular (bt.601) pixels 1 = square pixels 0 b 6 freeze output timing enable setting this bit to a ?1? freezes the output timing at the end of the field. resetting this bit to a ?0? resumes normal operation at the start of the next field. 0 = normal operation 1 = freeze output timing 0 b 5 dvalid duty cycle control (dvld_dcyc) this bit is ignored during the 8-bit ycbcr and bt.656 output modes. during 16-bit ycbcr, 15-bit rgb, or 16-bit rgb output modes, this bit is defined as: 0 = dvalid has 50/50 duty cycle at the pixel output data rate 1 = dvalid goes active based on line-lo ck. this will cause dvalid to not have a 50/50 duty cycle. this bit is intended to be used in main taining backward compatibility with the hmp8112a dvalid output timing. 0 b 4 dvalid line timing control (dvld_ltc) during 16-bit ycbcr, 15-bit rgb, or 16-bit rgb output modes, this bit is defined as: 0 = dvalid present only during active video time on active scan lines 1 = dvalid present the entire scan line time on all scan lines during the 8-bit ycbcr and bt.656 output modes, this bit defines the dvalid output as: 0 = normal timing 1 = dvalid signal anded with clk2 0 b 3 missing hsync detect select this bit specifies the number of missing horizontal sync pulses before entering horizontal lock acquisition mode. 0 = 12 pulses 1 = 1 pulse 1 b 2 missing vsync detect select this bit specifies the number of missing vertical sync pulses before entering vertical lock acquisition mode. 0 = 3 pulses 1 = 1 pulse 0 b 1-0 clk2 frequency this bit indicates the frequency of the clk2 input clock. 00 = 24.54mhz10 = 29.5mhz 01 = 27.0mhz11 = reserved 01 b HMP8117 25 table 16. analog input control register sub address = 05 h bit no. function description reset state 7-6 lock loss video gain select if bits 5-4 do not equal ?01?, these bits indicate what mode the agc circuitry will be after loss of sync. if bits 5-4 equal ?01? , these bits are ignored. 00 = automatic gain control: bits 5-4 will be reset to ?01? 01 = maintain fixed gain: bits 5-4 will not be changed 10 = normal agc switching to fixed gain after lock achieved: bits 5-4 will not be reset to ?01? unless they indicated ?freeze automatic gain control? 11 = reserved 00 b 5-4 video gain control select 00 = fixed 1x gain 01 = automatic gain control 10 = fixed gain control. (use gain factor from video gain adjust register 1d h .) 11 = freeze automatic gain control 01 b 3 digital anti-alias filter control 0 = internal digital anti-alias filter is active. 1 = internal digital anti- alias filter is bypassed. (not recommended) 0 b 2-0 video signal input select 000 = cvbs1 001 = cvbs2 010 = cvbs3 011 = s-video 1xx = reserved 000 b table 17. color processing register sub address = 06 h bit no. function description reset state 7-6 digital color gain control select 00 = no gain control (gain = 1x) 01 = automatic gain control 10 = fixed gain control. (use gain factor from color gain adjust register 1c h .) 11 = freeze automatic gain control 01 b 5-4 color killer select 00 = force color on 01 = enable color killer 10 = reserved 11 = force color off 01 b 3-2 color coring select coring may be used to reduce low-level noise in the cbcr signals. 00 = no coring 01 = 1 code coring 10 = 2 code coring 11 = 3 code coring 00 b 1 contrast control select this bit specifies whether the contrast control affects just the y data (?0?) or both the y and cbcr data (?1?). to avoid color shifts when c hanging contrast, this bit should be a ?1?. 0 = contrast controls only y data 1 = contrast controls y and cbcr data 1 b 0 color low-pass filter select this bit selects the bandwidth of the cbcr data. 0 = 850khz 1 = 1.5mhz 0 b HMP8117 26 table 18. luma processing register sub address = 08 h bit no. function description reset state 7-6 y filtering select the chroma trap filter may be used to remove any residual color subcarrier information from the y channel. during s-video operation, it should be disabled. during pal operation, it should be enabled. the 3mhz low-pass filter may be used to remove high-frequency noise. 00 = no filtering 01 = enable chroma trap filter 10 = enable 3.0mhz low-pass filter 11 = reserved 00 b 5-4 black level y coring select coring may be used to reduce low-level noise around black in the y signal. 00 = no coring 01 = 1 code coring 10 = 2 code coring 11 = 3 code coring 00 b 3-2 high frequency y coring select coring may be used to reduce high-frequency low-level noise in the y signal. 00 = no coring 01 = 1 code coring 10 = 2 code coring 11 = 3 code coring 01 b 1-0 sharpness frequency select specifies the amount of sharpness to be appl ied per the sharpness adjust register 1e h . 00 = bypass sharpness control10 = maximum gain at color f sc 01 = maximum gain at 2.6mhz11 = reserved 00 b table 19. sliced vbi da ta enable register sub address = 0a h bit no. function description reset state 7-6 sliced closed captioning enable 00 = closed caption disabled 01 = closed caption enabled for odd fields: line 21 for ntsc, line 18 for (m) pal, or line 22 for (b, d, g, h, i, n, n c ) pal 10 = closed caption enabled for even fields: li ne 284 for ntsc, line 281 for (m) pal, or line 335 for (b, d, g, h, i, n, n c ) pal 11 = closed caption enabled for both odd and even fields 00 b 5-4 sliced wss enable 00 = wss disabled 01 = wss enabled for odd fields: line 20 for ntsc; li ne 17 for (m) pal, or line 23 for (b, d, g, h, i, n, n c ) pal 10 = wss enabled for even fields: line 283 for ntsc , line 280 for (m) pal, or line 336 for (b, d, g, h, i, n, n c ) pal 11 = wss enabled for both odd and even fields 00 b 3-2 sliced teletext enable 00 = teletext disabled10 = teletext system c enabled 01 = teletext system b enabled11 = teletext system d enabled 00 b 1-0 reserved 00 b HMP8117 27 table 20. sliced vbi data output register sub address = 0b h bit no. function description reset state 7 sliced closed caption bt.656 output enable if set to ?1?, this bit enables output of sl iced closed captioning vi a bt.656 ancillary data. closed captioning must be enabled by t he sliced vbi data enable register 0a h . access via the i 2 c interface is always available. 0 b 6 sliced wss bt.656 output enable if set to ?1?, this bit enables output of sliced wss via bt.656 ancillary data. wss must be enabled by the sliced vbi data enable register 0a h . access via the i 2 c interface is always available. 0 b 5 sliced teletext bt.656 output enable if set to ?1?, this bit enables output of sliced teletext via bt.656 ancillary data. teletext data is not available via the i 2 c interface. 0 b 4-1 reserved 0000 b 0 rtci bt.656 output enable if set to ?1?, this bit enables output of rtci data as bt.656 ancillary data. 0 b table 21. vbi data status register sub address = 0c h bit no. function description reset state 7 cc odd field detect status this bit is read-only. data wr itten to this bit is ignored. if set to ?1?, closed captioning (cc) data is detected on the odd field. 0 b 6 cc even field detect status this bit is read-only. data wr itten to this bit is ignored. if set to ?1?, closed captioning (cc) data is detected on the even field. 0 b 5 wss odd field detect status this bit is read-only. data wr itten to this bit is ignored. if set to ?1?, wide screen signalling (wss) data is detected on the odd field. 0 b 4 wss even field detect status this bit is read-only. data wr itten to this bit is ignored. if set to ?1?, wide screen signalling (wss) data is detected on the even field. 0 b 3 vbi teletext detect status this bit is read-only. data wr itten to this bit is ignored. if set to ?1?, teletext data is detect ed during the vertical blanking interval. 0 b 2-0 reserved 000 b HMP8117 28 table 22. video status register sub address = 0e h bit no. function description reset state 7 vertical lock status this bit is read-only. data wr itten to this bit is ignored. if set to ?1?, the decoder is vertically locked to the input signal. 0 b 6 horizontal lock status this bit is read-only. data wr itten to this bit is ignored. if set to ?1?, the decoder is horiz ontally locked to the input signal. 0 b 5 color lock status this bit is read-only. data wr itten to this bit is ignored. if set to ?1?, the decoder is chroma locked to the input signal. 0 b 4 input video detect status this bit is read-only. data wr itten to this bit is ignored. if set to ?1?, video is detected on the input signal. 0 b 3-1 mv detection status these bits are read-on ly. data written to this bit is ignored. 000 b = no mv present 001 b = psp present, no stripes 010 b = psp present, 2-line stripes 011 b = psp present, 4-line stripes 100 b = reserved 101 b = reserved 110 b = no psp present, 2-line stripes (invalid mv scheme, may indicate false detection) 111 b = no psp present, 4-line stripes (invalid mv scheme, may indicate false detection) 000 b 0 auto detect video standard status this bit is read-only. data wr itten to this bit is ignored. if set to ?1?, the decoder determined the video standard on the input signal. this bit is enabled by the input format register 01 h bit 4. 0 b table 23. interrupt mask register sub address = 0f h bit no. function description reset state 7 genlock loss interrupt mask if set to ?1?, an interrupt is enabled for the loss of genlock. 0 b 6 input signal loss interrupt mask if set to ?1?, an interrupt is enabled for the loss of input video signal. 0 b 5 closed caption interrupt mask if set to ?1?, an interrupt is enabled for new data in the closed caption data registers. 0 b 4wss interrupt mask if set to ?1?, an interrupt is enabled for new data in the wss data registers. 0 b 3 teletext interrupt mask if set to ?1?, an interrupt is enabled for the detection of teletext data in the current field. 0 b 2 mv interrupt mask if set to ?1?, an interrupt is enabled for a change in the mv detection status register 0e h .0 b 1 auto detect video standard interrupt mask if set to ?1?, an interrupt is enabled for the successful auto detection of a video standard. 0 b 0 vertical sync interrupt mask if set to ?1?, an interrupt is enabled for the start of a new field. 0 b HMP8117 29 table 24. interrupt status register sub address = 10 h bit no. function description reset state 7 genlock loss interrupt status if set to ?1?, this bit indicates the interrupt request was due to a loss of genlock. to clear the interrupt request, a ?1? must be written to this bit. 0 b 6 input signal loss interrupt status if set to ?1?, this bit indicates the interrupt request was due to a loss of input video signal. to clear the interrupt request, a ?1? must be written to this bit. 0 b 5 closed caption interrupt status if set to ?1?, this bit indicates the interrupt reques t was due to new data in the closed caption data registers. to clear the interrupt request, a ?1? must be written to this bit. 0 b 4 wss interrupt status if set to ?1?, this bit indicates the interrupt r equest was due to new data available in the wss data registers. to clear the interrupt request, a ?1? must be written to this bit. 0 b 3 teletext interrupt status if set to ?1?, this bit indicates the interrupt request was due to the detection of teletext data in the current field. to clear the interrupt request, a ?1? must be written to this bit. 0 b 2 mv interrupt status if set to ?1?, this bit indicates the in terrupt request was due to a change in the mv detection status of register 0e h . to clear the interrupt request, a ?1? must be written to this bit. 0 b 1 auto detect video standard interrupt status if set to ?1?, this bit indicates the interrupt request was due to the successful auto detection of a video standard. to clear the interrupt request, a ?1? must be written to this bit. 0 b 0 vertical sync interrupt status if set to ?1?, this bit indicates the interrupt request was due to the start of a new field. to clear the interrupt request, a ?1? must be written to this bit. 0 b table 25. raw vbi control register sub address = 11 h bit no. function description reset state 7-4 reserved 0000 b 3 raw preamble enable if set to ?1?, enables a four byte preamble in the raw vbi data stream. the preamble format is ff h , cnt1, cnt2 and 00h, where: cnt1: bit 7 = even parity bar, bit 6 = even parity[5-0], bit 5 = 0, bit 4 = field (0=odd, 1=even), bits 3 -0 =linecount[8-4]. cnt2: bit 7 = even parity bar, bit 6 = even parity [5-0], bits 5-4 = 00 bits 3-0 = linecount[3-0]. 0 b 2 raw vbi all if set to ?1?, all the video lines (full field) are converted to raw vbi data. if set to ?0?, only the lines enabled by the raw vbi line mask registers are converted to raw vbi data. 0 b 1 raw vbi even field if set to ?1?, even field lines are converted to raw vbi data as specified by the raw vbi all bit and the raw vbi line mask registers. if set to ?0?, the even field lines are excluded from the raw vbi data stream. 0 b 0 raw vbi odd field if set to ?1?, odd field lines are converted to ra w vbi data as specified by the raw vbi all bit and the raw vbi line mask registers. if set to ?0?, the odd field lines are excluded from the raw vbi data stream. 0 b HMP8117 30 table 26. raw vbi start count register sub address = 12 h bit no. function description reset state 7-0 raw vbi start count specifies the start of the raw vbi data sampling window in two clk2 period steps from the leading edge of hsync. 7a h table 27. raw vbi stop count lsb register sub address = 13 h bit no. function description reset state 7-0 raw vbi stop count lsb this 8-bit register is cascaded with raw vbi st op count msb (below) to form a 10-bit stop count value. the stop count specifies the end of the raw vbi data sampling window in two clk2 period steps from the leading edge of hsync. 4a h table 28. raw vbi stop count msb register sub address = 14 h bit no. function description reset state 7-2 reserved 000000 b 1-0 raw vbi stop count msb this 2-bit register is cascaded with raw vbi stop count lsb (above) to form a 10-bit stop count value. the stop count specifies the end of the raw vbi data sampling window in two clk2 period steps from the leading edge of hsync. 11 b table 29. raw vbi line mask_7_0 register sub address = 15 h bit no. function description reset state 7-0 raw vbi line mask_7_0 a ?1? in each bit position enables raw vbi captur e for a corresponding input video line. refer to table 32 below. fe h table 30. raw vbi line mask_15_8 register sub address = 16 h bit no. function description reset state 7-0 raw vbi line mask_15_8 a ?1? in each bit position enables raw vbi captur e for a corresponding input video line. refer to table 32 below. 1f h table 31. raw vbi line mask_18_16 register sub address = 17 h bit no. function description reset state 7-3 reserved 00000 b 2-0 raw vbi line mask_18_16 a ?1? in each bit position enables raw vbi captur e for a corresponding input video line. refer to table 32 below. 000 b HMP8117 31 table 32. raw vbi mask definitions mask (register = default) mask_18_16 (reg. 17 h ) mask_15_8 (register 16 h ) mask_7_0 (register 15 h ) register bit 2107654321076543210 mask bit 18 17 16 15 14 13 12 11 10 9 8 76543210 ntsc (odd) line# 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ntsc (even) line# 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 pal (odd) line#232221201918171615141312111098765 pal (even) line# 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 table 33. brightness register sub address = 18 h bit no. function description reset state 7 reserved 0 b 6-0 brightness adjust these bits control the brightnes s. they may have a value of +63 (?011 1111?) to -64 (?100 0000?), with positive values increasi ng brightness. a value of 0 (?000 0000?) has no effect on the data. 0000000 b table 34. contrast register sub address = 19 h bit no. function description reset state 7-0 contrast adjust these bits control the contrast. they may hav e a value of 0x (?0000 0000?) to 1.992x (?1111 1111?). a value of 1x (?1000 0000?) has no effect on the data. 80 h table 35. hue register sub address = 1a h bit no. function description reset state 7-0 hue adjust these bits control the color hue. they may have a value of +30 degrees (?0111 1111?) to -30 degrees (?1111 1111?). a value of 0 degrees (?0000 0000?) has no effect on the color data. 00 h table 36. saturation register sub address = 1b h bit no. function description reset state 7-0 saturation adjust these bits control the color saturation. they may have a value of 0x (?0000 0000?) to 1.992x (?1111 1111?). a value of 1x (?1000 0000?) has no effect on the color data. a value of 0x (?0000 0000?) disables the color information. 80 h table 37. color gain adjust register sub address = 1c h bit no. function description reset state 7-0 color gain adjust these bits control the amount of digi tal gain applied to the color difference (cbcr) signals. they may have a value of 0.5x (?0010 0000?) to 3.98x (?1111 1111?). a value of 1x (?0100 0000?) has no effect on the data. this register enabled by the selection of ?fixed gain control? mode in the color processing register 06 h . 40 h HMP8117 32 table 38. video gain adjust register sub address = 1d h bit no. function description reset state 7-0 video gain adjust this register is enabled by the select ion of ?fixed gain control? mode in the analog input control register 05 h bits 7-4. the value of this register selects a combined analog attenuation and a digital gain factor which is applied to both luma and chroma input channels. the gain factor is selected from nonlinear lookup table and may range in value from 0.5x (ce h ) to 1.99x (33 h ). refer to table 39 below. the register values in italics below mark the approximate analog attenuation ladder switching points. 80 h table 39. video gain register lookup table video gain reg. value video gain reg. value video gain reg. value video gain reg. value video gain reg. value video gain reg. value 0.50 0.51 0.52 0.53 0.54 0.55 206/ceh 202/ca h 197/c5 h 193/c1 h 191/bf h 187/bb h 0.67 0.68 0.69 0.70 0.71 0.72 153/99 h 151/97 h 150/96h 147/93 h 145/91 h 143/8f h 0.84 0.85 0.86 0.87 0.88 0.89 123/7b h 121/79 h 119/77 h 118/76 h 117/75 h 115/73h 1.03 1.04 1.05 1.06 1.07 1.08 100/64 h 99/63 h 98/62 h 97/61 h 96/60 h 95/5f h 1.23 1.25 1.27 1.28 1.30 1.31 83/53 h 82/52 h 81/51 h 80/50 h 79/4f h 78/4e h 1.55 1.57 1.59 1.63 1.65 1.67 66/42 h 65/41 h 64/40 h 63/3f h 62/3e h 61/3d h 0.56 0.57 0.58 0.59 0.60 0.61 183/b7 h 180/b4 h 178/b2 h 174/ae h 171/ab h 169/a9 h 0.73 0.74 0.75 0.76 0.77 0.78 141/8d h 139/8b h 137/89 h 136/88 h 134/86 h 132/84h 0.90 0.91 0.92 0.94 0.95 0.96 114/72 h 113/71 h 111/6f h 110/6e h 109/6d h 107/6b h 1.09 1.10 1.12 1.13 1.14 1.15 94/5e h 93/5d h 92/5c h 91/5b h 90/5a h 89/59 h 1.33 1.34 1.37 1.38 1.40 1.42 77/4dh 76/4c h 75/4b h 74/4a h 73/49 h 72/48 h 1.70 1.73 1.76 1.79 1.82 1.86 60/3c h 59/3bh 58/3a h 57/39 h 56/38 h 55/37 h 0.62 0.63 0.64 0.65 0.66 167/a7 h 164/a4 h 161/a1 h 159/9f h 156/9c h 0.79 0.80 0.81 0.82 0.83 130/82 h 128/80 h 126/7e h 125/7d h 124/7c h 0.97 0.98 1.00 1.01 1.02 106/6a h 104/68 h 103/67 h 102/66 h 101/65h 1.16 1.18 1.20 1.21 1.22 88/58h 87/57 h 86/56 h 85/55 h 84/54 h 1.44 1.46 1.48 1.51 1.52 71/47 h 70/46 h 69/45 h 68/44h 67/43 h 1.89 1.93 1.97 1.99 54/36 h 53/35 h 52/34 h 51/33h table 40. sharpness adjust register sub address = 1e h bit no. function description reset state 7-6 reserved 00 b 5-0 sharpness adjust specifies the amount of high frequency gain contro l for luminance signals (either 2.6mhz or f sc ), as determined by the luma processing register 08 h . the gain ranges from +12db (11 1111 b ) to -12db (00 0100 b ). a value of 0db (?01 0000?) has no effect on the data. 010000 b HMP8117 33 table 41. host control register sub address = 1f h bit no. function description reset state 7 software reset when this bit is set to 1, the entire device except the i 2 c bus is reset to a known state exactly like the reset input going active. the software reset will in itialize all register bits to their reset state. once set this bit is self clearing. this bit is cleared on power-up by the external reset pin. 0 b 6 power down when this bit is set to a 1, the entire device is shut down except the i 2 c bus by gating off the clock. for normal decoding operati ons this bit should be set to a 0. 0 b 5 closed caption odd field read status this bit is read-only. data writt en to this bit is ignored. the bit is cleared when the caption data has been read out via the i 2 c interface or as bt.656 ancillary data. 0 = no new caption data 1 = caption_odd_a and caption_odd_b data registers contain new data. 0 b 4 closed caption even field read status this bit is read-only. data writt en to this bit is ignored. the bit is cleared when the caption data has been read out via the i 2 c interface or as bt.656 ancillary data. 0 = no new caption data 1 = caption_even_a and caption_even_b data registers contain new data. 0 b 3wss odd field read status this bit is read-only. data written to this bit is ignored. the bit is cleared when the wss data has been read out via the i 2 c interface or as bt.656 ancillary data. 0 = no new wss data 1 = wss_odd_a and wss_odd_b data registers contain new data. 0 b 2wss even field read status this bit is read-only. data written to this bit is ignored. the bit is cleared when the wss data has been read out via the i 2 c interface or as bt.656 ancillary data. 0 = no new wss data 1 = wss_even_a and wss_even_b data registers contain new data. 0 b 1-0 reserved 00 b table 42. closed caption_odd_a data register sub address = 20 h bit no. function description reset state 7-0 odd field caption data if odd field captioning is enabled and present, this regi ster is loaded with the first eight bits of caption data on line 18, 21, or 22. bit 0 corresponds to the first bit of caption information. data written to this register is ignored. 80 h table 43. closed caption_odd_b data register sub address = 21 h bit no. function description reset state 15-8 odd field caption data if odd field captioning is enabled and present, this regi ster is loaded with the second eight bits of caption data on line 18, 21, or 22. data written to this register is ignored. 80 h table 44. closed captio n_even_a data register table 45. sub address = 22 h bit no. function description reset state 7-0 even field caption data if even field captioning is enabled an d present, this register is loaded with the first eight bits of caption data on line 281, 284, or 335. bit 0 corresponds to the first bit of caption information. data written to this register is ignored. 80 h HMP8117 34 table 46. closed captio n_even_b data register sub address = 23 h bit no. function description reset state 15-8 even field caption data if even field captioning is enabled and present, this register is loa ded with the second eight bits of caption data on line 281, 284, or 335. data written to this register is ignored. 80 h table 47. wss_odd_a data register sub address = 24 h bit no. function description reset state 7-0 odd field wss data if odd field wss is enabled and present, this register is loaded with the first eight bits of wss information on line 17, 20, or 23. bit 0 corresponds to the first bit of wss information. data written to this register is ignored. 00 h table 48. wss_odd_b data register sub address = 25 h bit no. function description reset state 15-14 reserved 00 b 13-8 odd field wss data if odd field wss is enabled and present, this register is loaded with the second six bits of wss information on line 17, 20, or 23. data written to this register is ignored. 000000 b table 49. wss_crc_odd data register sub address = 26 h bit no. function description reset state 7-6 reserved 00 b 5-0 odd field wss crc data if odd field wss is enabled and present during ntsc operation, this regist er is loaded with the six bits of crc information on line 20. it is al ways a ?000000? during pal operation. data written to this register is ignored. 000000 b table 50. wss_even_a data register sub address = 27 h bit no. function description reset state 7-0 even field wss data if even field wss is enabled and present, this regist er is loaded with the fi rst eight bits of wss information on line 280, 283, or 336. bit 0 correspon ds to the first bit of wss information. data written to this register is ignored. 00 h table 51. wss_even_b data register sub address = 28 h bit no. function description reset state 15-14 reserved 00 b 13-8 even field wss data if even field wss is enabled and pres ent, this register is loaded with the second six bits of wss information on line 280, 283, or 336. data written to this register is ignored. 000000 b HMP8117 35 table 52. wss_crc_even data register sub address = 29 h bit no. function description reset state 7-6 reserved 00 b 5-0 even field wss crc data if even field wss is enabled and pres ent during ntsc operation, this register is loaded with the six bits of crc information on line 283. it is alwa ys a ?000000? during pal operation. data written to this register is ignored. 000000 b table 53. start h_blank lsb register sub address = 30 h bit no. function description reset state 7-0 assert blank output signal this 8-bit register is cascaded with start h_blan k high register to form a 10-bit start horizontal blank register. it specifies the horizontal count (i n 1x clock cycles) at which to assert blank each scan line. bit 0 is always a ?0?, so the star t of horizontal blanking may only be done with two pixel resolution. the leading edge of hsync is count 000 h . 4a h table 54. start h_blank msb register sub address = 31 h bit no. function description reset state 15-10 reserved 000000 b 9-8 assert blank output signal this 2-bit register is cascaded with start h_blan k low register to form a 10-bit start horizontal blank register. it specifies the hor izontal count (in 1x clock cycle s) at which to assert blank each scan line. the leading edge of hsync is count 000 h . 11 b table 55. end h_blank register sub address = 32 h bit no. function description reset state 7-0 negate blank output signal this 8-bit register specifies the horizontal count (in 1x clock cycles) to negate blank each scan line. for proper operation, bit 0 must always be set to ?0?; therefore, the end of horizontal blanking may only set with two pixel resolution. if bit 0 is set to ?1?, the chroma/luma output data may be swapped. the leading edge of hsync is count 000 h . 7a h table 56. start v_blank lsb register sub address = 33 h bit no. function description reset state 7-0 assert blank output signal this 8-bit register is cascaded with start v_blan k high register to form a 9-bit start vertical blank register. it specifies the line number to assert blank each field. for ntsc operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. for pal operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields. 02 h table 57. start v_blank msb register sub address = 34 h bit no. function description reset state 15-9 reserved 0000000 b 8 assert blank output signal this 1-bit register is cascaded with start v_blan k low register to form a 9-bit start vertical blank register. 1 b HMP8117 36 table 58. end v_blank register sub address = 35 h bit no. function description reset state 7-0 negate blank output signal this 8-bit register specifies the line number to negate blank each field. for ntsc operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. for pal operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields. 12 h table 59. end hsync register sub address = 36 h bit no. function description reset state 7-0 negate hsync output signal this 8-bit register specifies the hor izontal count at which to negate hsync each scan line. values may range from 0 (0000 0000) to 510 ( 1111 1111) clk2 cycles. the leading edge of hsync is count 00 h . 30 h table 60. hsync detect window register sub address = 37 h bit no. function description reset state 7-0 horizontal sync detect window this 8-bit register specifies the width of the ti ming window (in 1x clock samples) for the digital pll to accept horizontal sync pulses in each line. the window is centered about where the horizontal sync pulse should be located. if the horizontal sync pulse falls inside the window , the digital pll maintains normal lock timing. if the horizontal sync pulse falls outside this window, the digi tal pll will to enter the horizontal lock acquisition mode based on the current setting for bits 3-2 of register 04 h . recommend changing this register to 90 h following reset in order to widen the window for poorly timed input video sources. 20 h (use 90 h ) table 61. mv control sub address = 41 h bit no. function description reset state 7 mv stripe detection and bypass enable set to ?1? to enable the detection and bypass of the mv color striping component. if this bit is not enabled and the mv color striping component ex ists on the input signal, artifacts will be clearly visible as horizontal streaks in the out put data. this bit must be enabled for the mv detection status of register 0e h to be updated. 0 b 6 mv psp detection enable set to ?1? to enable detection of the mv pseudo sync pulse (psp) component. if the mv psp component exists on the input signal, this bit must be enabled for the mv detection status of register 0e h to be updated. 0 b 5-3 mv psp detection count defines the number of extra syn c pulses required before declaring the pseudo sync pulse (psp) component in the mv detection status of register 0e h . the psp component must also be present for the number of fields defined in bits 2-0 below. 100 b 2-0 mv detection field count defines the minimum number of fields that an mv component must be present for in order to change the mv detection status of register 0e h . add 2 to bits 2-0 to obtain the minimum field count. ex: the default of 110 b is actually 6 + 2 = 8 fields. 110 b table 62. reserved sub address = 42 h bit no. function description reset state 7-0 reserved set bits 5-4 to 11 b for optimum performance. 00 h (use 30 h ) HMP8117 37 table 63. programmable fractional gain sub address = 50 h bit no. function description reset state 7-6 reserved set to 00 b for proper operation. 00 b 5 select pfg enable set to ?1? to enable t he recommended pfg value in bits 4-0 below. 0 b (use 1 b ) 4-0 pfg programmable fractional gain (pfg). when enabled by bit 5, changes the loop gain (response time) of the agc logic. slower values provide some noise imm unity to input signals with poor sync/back-porch characteri stics. recommend using the slowest pfg value of 00001 b for optimum performance. (thus the recommended 8-bit register value = 21 h ). the 5-bit pfg value has a fr actional representation as: 2 0 . 2 -1 2 -2 2 -3 2 -4 sample pfg values: 00000 b : gain = 0.0000 (freezes agc at current value) 00001 b : gain = 0.0625 (slowest agc response time -- recommended pfg) 01100 b : gain = 0.7500 (default) 10000 b : gain = 1.0000 11111 b : gain = 1.9375 (fastest agc response time -- not recommended) 01100 b (use 01 h ) table 64. mv stripe gate sub address = 51 h bit no. function description reset state 7-6 reserved set to 00 b for proper operation. 00 b 5-0 mv stripe gate defines the start of the gate for mv color stripe detection in 4xf sc counts. the gate should start prior to the chroma burst. default value of 010100 b (14 h ) is valid for ntsc. recommend 100000 b (20 h ) for pal. 010100 b table 65. reserved sub address = 52 h bit no. function description reset state 7-0 reserved set bit 5 to ?1? for optimum performance. 02 h (use 22 h ) table 66. agc hysteresis sub address = 53 h bit no. function description reset state 7-4 defines the amount of hysteresis in the agc l ogic. larger hysteresis values stabilize the agc with poor quality input signals. for example: 0000 b = no hysteresis 1000 b = default hysteresis 1111 b = maximum hysteresis (r ecommended hysteresis value) 1000 b (use f0 h ) 3-0 reserved set to 0000 b for proper operation. 0000 b table 67. device revision sub address = 7f h bit no. function description reset state 7-0 device revision this 8-bit r egister specifies the device revision number. da ta written to this read-only register is ignored. the production basel ine revision number is 01 h . 01 h HMP8117 38 pinout 80 lead pqfp top view 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 agnd v aa agnd cvbs1 nc cvbs3(y) cvbs2 agnd v aa agnd y out agnd v aa nc y in 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 p13 v cc p12 p11 p10 p9 p8 gnd v cc p7 p6 p5 p4 p3 gnd p2 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 gnd vcc ref_cap nc lcap vcc nc gnd hsync vsync gnd vcc dvalid a/d_test nc c nc 63 62 61 p 1 5 g n d v b i v a l i d 37 38 39 40 gnd intreq p1 p0 scl 44 43 42 41 17 18 19 20 80 agnd nc field p 1 4 blank agnd agnd agnd agnd agnd v cc sa rset ccap nc v cc nc gnd reset gnd gnd v cc clk2 gnd sda pin descriptions pin name pin number i/o passive description cvbs1, cvbs2, cvbs3(y) 7, 6, 5 i 75 ? term, 1 f ac-coupled composite video inputs. cvbs3(y) is the luminance (y) signal in s-video mode. these inputs must each be terminated by a 75 ? resistor to agnd and ac-coupled by a 1.0 f capacitor as shown in the reference schem atic. these components should be as close to this pin as possible for best performance. if not used, this pin should be connected to agnd through a 0.1 f capacitor. yout 9 o external anti- alias filter analog output of the video multiplexer. a exte rnal low-pass anti-alias filter between the yout and yin pins, as shown in the referenc e schematic. the filter components should be as close as possible to the yo ut and yin pins for best performance. yin 8 i analog input to the adc. see yout description above. c19 i 75 ? term, 1 f ac-coupled and external anti- alias filter chrominance (c) s-video input. this input must each be terminated by a 75 ? resistor to agnd and ac-coupled by a 1.0 f capacitor as shown in t he reference schematic. these components, and the corresponding anti-alias low-pa ss filter, should be as close to this pin as possible for best perform ance. if not used, this pi n should be connected to agnd through a 0.1 f capacitor. a/d test 17 o none chroma signal a/d test pin. this pin must be left floating for proper operation. rset 28 o 12.1k ? to agnd a 12.1k ? resistor must be connected between this pi n and agnd. this resistor should be as close to this pin as possible for best perform ance. the function of this pin has changed from the hmp8112a/15 gain_cntrl input. do not us e capacitor decoupling for this output pin. ref_cap 78 o 1.0f to agnd voltage reference capacitor. a 1f ceramic capacitor must be connected between this pin and agnd. this capacitor should be as close to this pin as possible for best performance. HMP8117 39 lcap 76 i 0.1f to agnd storage capacitor for luminance signal dc rest oration. the lcap voltage offsets the sync tip to the lower reference of the a/d. a 0.1 f capacitor should be connected between this pin and agnd. this capacitor should be as close to this pin as possible for best performance. ccap 29 i 0.1f to agnd storage capacitor for chrominance signal dc restoration. the ccap voltage offsets the chroma signal to mid-range of the a/d. a 0.1 f capacitor should be connected between this pin and agnd. this capacitor should be as close to this pi n as possible for best performance. p0-p15 42, 43, 45, 47-51, 54-58, 60, 63, 64 on/a pixel output pins. see table 3. these pins are three-stated after a reset or software reset. hsync 71 o 10k ? pullup horizontal sync output. hsync is asserted during the horiz ontal sync intervals. the polarity of hsync is programmable. this pin is three-stated after a reset or software reset and should be pulled high through a 10k ? resistor. vsync 70 o 10k ? pullup vertical sync output. vsync is asserted during the vertical sync intervals. the polarity of vsync is programmable. this pin is three-stated after a reset or software reset and should be pulled high through a 10k ? resistor. field 67 o 10k ? pullup field output. the polarity of field is programmable. this pin is three-stated after a reset or software reset and should be pulled high through a 10k ? resistor. dvalid 66 o 10k ? pullup data valid output. dvalid is asserted during clk2 cycles that contain valid pixel data. this pin is three-stated after a reset or software reset and should be pulled high through a 10k ? resistor. blank 65 o 10k ? pullup composite blanking output. blank is asserted during the horizontal and vertical blanking intervals. the polarity of blank is programmable. this pin is three-stated after a reset or software reset and should be pulled high through a 10k ? resistor. vbivalid 61 o 10k ? pullup vertical blanking interval valid output. vbivalid is asserted during clk2 cycles that contain valid vbi (vertical blanking interval) dat a such as closed captioning, teletext, and wss data. the polarity of vbivalid is programmable. this pin is three-stated after a reset or software reset and should be pulled high through a 10k resistor. intreq 44 o 10k ? pullup interrupt request output. this is an open-drain output and requires an external 10k ? pull- up resistor to v cc . clk2 38 i 2x pixel clock input. this clock must be a c ontinuous, free-running clock. refer to table 1 for allowable clk2 frequencies for each video standard and aspect ratio. for best performance, use termination resistor(s) to minimize pulse over shoot and reflections. reset 34 i reset control input. a logical zero for a mini mum of four clk2 cycles resets the device. reset must be a logical one for normal operation. sa 27 i 10k ? pullup or 0 ? pulldown i 2 c slave address select input. this was form erly the wpe pin on hmp8112/15 decoders. if the sa pin is pulled low, the i 2 c address is 1000100xb or 88 h . if the sa pin is pulled high, the address is 1000101xb or 8a h . (the ?x? bit is the address is the i2c read flag.) sda 40 i/o 4k ? pullup i 2 c data input/output. this pin should be pulled high through a 4k ? resistor. scl 41 i 4k ? pullup i 2 c clock input. this pin should be pulled high through a 4k ? resistor. vaa 2, 12, 14 i 0.1f to agnd analog power supply pins. all vaa pins must be connected together. agnd 1, 3, 10, 11, 15,16, 21, 22, 23, 24 i none analog ground pins. all agnd pins must be c onnected together. refer to applications section for recommended grounding scheme. vcc 26, 31,37, 52, 59, 68, 75, 79 i digital power supply pins. all v cc pins must be connected together. gnd 25, 33, 35, 36, 39, 46, 53, 62, 69, 72, 80 i digital ground pins. all gnd pi ns must be connected together. nc 4, 13, 18, 20, 30, 32, 73, 74, 77 no connect pins. these pins may be left floating or tied to gnd. pin descriptions (continued) pin name pin number i/o passive description HMP8117 40 applications information direct interface to video encoders direct interface to a video encoder will induce pixel jitter in the output video and is ther efore not recommended as a primary data interface. the jitt er will occur with all decoder output formats, including bt.656. however, pixel jitter may be acceptable for some applications; such as a ?preview mode? prior to image capture or compression. for more detail, reference ?cycle slipping and real-time pixel jitter? section fr om this data sheet. decoder upgrades the following table describe the impacts to pins for upgrading from the hmp8112/a or hmp8115 to the HMP8117. typical programming sequence the following pseudo code provides a typical programming sequence to initialize the hmp 8117 using the default 16-bit ycbcr output data format. setreg 0x1f = 0x80 // soft reset setreg 0x37 = 0x90 // wider hsync detect window setreg 0x42 = 0x30 // recommended value setreg 0x50 = 0x21 // slower pfg setreg 0x52 = 0x22 // recommended value setreg 0x53 = 0xf0 // large agc hysteresis setreg 0x03 = 0xc0 // enable data/timing outputs pcb layout considerations a pcb board with a minimum of 4 layers is recommended, with layers 1 and 4 (top and bottom) for signals and layers 2 and 3 for power and ground. the pcb layout should implement the lowest possible noise on the power and ground planes by providing excellent decoupling. the optimum layout places the hm p8117 as close as possible to the power supply connector and the video input connector. place external com ponents as close as possible to the appropriate pin using short, wide traces. analog power plane the analog power plane (v aa ) is recommended to be separate from the common board digital power plane (v cc ) with a gap between the two planes of at least 1/8 inch. the v aa plane should be connected to the v cc plane at a single point though a low-resistance ferrite bead, such as a ferroxcube 5659065-3b, fair-rite 2743001111, or tdk bf45-4001. the ferrite bead provides resistance to switching currents, improving the performance of HMP8117. if a separate linear regulator is used to provide power to the analog power plane, the power-up sequence should be designed to ensure latch up will not occur. a separate linear regulator is recommended if the power supply noise on the v aa pins exceeds 200mv. analog ground plane a separate analog ground (ag nd) plane is recommended with a single point connection to the digital ground (gnd) plane using a ferrite bead as mentioned above. power supply decoupling decouple each v aa and v cc pin to the appropriate ground plane using a 0.1 f ceramic chip capacitor. bulk decouple the power planes using a 1.0 f ceramic chip capacitor located at each corner of the device. (one capacitor placed at the top left corner for v aa and three capacitors placed at the other corners for v cc .) a single 47 f decoupling capacitor for the analog power plane may also be used to control excessive low-frequency power supply ripple. see figure 20, HMP8117 reference schematics. analog signals traces containing digital signals should not be routed over, under, or adjacent to the analog output traces to minimize cross-talk. if this is not possible, coupling can be minimized by routing the digital signals at a 90 degree angle to the analog signals. the analog traces should also not overlay the v cc power plane to maximize high-frequency power supply rejection. evaluation board hmpvideval/isa the hmpvideval/isa board prov ides a complete video frame-grabber platform to evaluate all modes of the video decoder and encoder. the isa style pc add-in board supports a complete windows 95 software application to easily operate all features of the evaluation platform. table 68. upgrading from hmp8112/a or hmp8115 pin # hmp8112/15 pin HMP8117 impact 28 gain_cntl (now rset) use single 12.1k resistor to agnd. remove any decoupling caps. 78 dec_t (now ref_cap) change to single 1.0uf capacitor (1206-size xr7-type) to agnd. 29 cclamp_cap (now ccap) change to 0.1uf capacitor. 76 lclamp_cap (now lcap) change to 0.1uf capacitor. 9,8,19 l_out, l_adin, and c recommend use of new anti-alias filter from reference schematic. 27 wpe (now sa) pull low for i2c address compatibility with hmp8112/a. 44 dvcc/nc (now intreq ) pin actually nc on hmp8112/a. float or use 10k pullup to vcc. 61 dgnd/nc (now vbivalid ) pin actually nc on hmp8112/a. float or use 10k pullup to vcc. 13 clk2 (now nc) trace may be deleted to reduce reflections on clk2 at pin 38. 30, 32, 73, 77 dec_l, dgnd, dgnd, agc_cap pins no longer used (nc). capacitors used at these pins may be removed. HMP8117 41 related application notes application notes are also available on the intersil multimedia web site at http ://www.intersil.com/mmedia. an9644 : composite video separation techniques an9716 : wide screen signalling an9717 : ycbcr to rgb considerations an9728 : bt.656 video interface for ics an9806 : advantages of the HMP8117 videolyzer operation r6 75 54 p15 p14 p13 p12 p11 p10 p9 p8 y in y out lcap ccap rset ref_cap cvbs1 cvbs2 cvbs3(y) c 7 6 5 19 8 9 78 c1 1.0 f 76 29 28 c11 1.0 f r8 12.1k c10 0.1 f c9 0.1 f r3 75 r2 75 r1 75 c2 1.0 f c3 1.0 f c6 1.0 f figure 20. HMP8117 reference schematics intreq v cc rp1 10k HMP8117 r4 324 r5 4.02k c5 47pf l1 8.2 h c4 22pf 324 c8 47pf 8.2 h c7 22pf r7 l2 55 56 57 58 60 63 64 42 p7 p6 p5 p4 p3 p2 p1 p0 43 45 47 48 49 50 51 hsync vsync field dvalid blank vbivalid intreq 44 vbivalid blank dvalid field vsync hsync 61 65 66 67 70 71 r9 4k r10 4k reset scl 34 clk2 scl sda 38 41 sda clk2 reset 40 p[15:0] vid1 vid2 y_in c_in v cc v cc sa 27 jp1: address select jumper luma anti-alias filter chroma anti-alias filter c19 0.1 f l3 c20 0.1 f c21 0.1 f c22 0.1 f c23 0.1 f c15 1.0 f c17 1.0 f c18 1.0 f c24 0.1 f c25 0.1 f c26 0.1 f l4 ferrite bead ferrite bead c16 1.0 f c12 0.1 f c13 0.1 f c14 0.1 f gnd v cc agnd v aa bot left bot right top right bulk decoupling digital - v cc decoupling analog - v aa decoupling pin 26 pin 31 pin 37 pin 52 pin 59 pin 68 pin 72 pin 79 top left pin 14 pin 12 pin 1 c27 47 f near ferrite 100 r11 series termination external 75 ? video sources from 75 ? source near clk2 source 75 75 75 HMP8117 42 absolute maximum rati ngs thermal information digital supply voltage (v cc to gnd) . . . . . . . . . . . . . . . . . . . . 7.0v analog supply voltage (vaa to gnd) . . . . . . . . . . . . . . . . . . . 7.0v digital input voltages . . . . . . . . . . . . . . . gnd - 0.5v to v cc + 0.5v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating temperature range HMP8117cn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, see note 40) ja ( o c/w) mqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 maximum power dissipation HMP8117cn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.78w maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum junction temperatures . . . . . . . . . . . . . . . . . . . . .150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 40. ja is measured with the component mounted on an evaluation pc board in free air. dissipation rating assumes device is mounted wit h all leads soldered to printed circuit board. electrical specifications v cc = v aa = 5.0v, t a = 25 o c parameter symbol test condition min typ max units power supply characteristics power supply voltage range v cc , v aa (note 2) 4.75 5 5.25 v total power supply current i tot clk2 = 29.5mhz, v cc = vaa = 5.25v outputs not loaded - 279 305 ma digital power supply current i cc - 132 - ma analog power supply current i aa - 147 - ma total power dissipation p tot - 1.46 1.60 w dc characteristics: digital i/o (except clk2 and i 2 c interface) input logic high voltage v ih v cc = max 2.0 - - v input logic low voltage v il v cc = min - - 0.8 v output logic high voltage v oh i oh = -4ma, v cc = max 2.4 - - v output logic low voltage v ol i ol = 4ma, v cc = min - - 0.4 v input leakage current i ih , i il v cc = max, input = 0v or 5v -10 - 10 a input/output capacitance c in , c out f = 1mhz (note 2) all measurements referenced to ground, t a = 25 o c -8-pf three-state output current leakage i oz -10 - 10 a dc characteristics: clk2 digital input input logic high voltage v ih v cc = max 0.7xv cc --v input logic low voltage v il v cc = min - - 0.3xv cc v input leakage current i ih v cc = max input = 0v or v cc -10 - 10 a i il - 450 - - a input capacitance c in clk2 = 1mhz (note 2) all measurements referenced to ground, t a = 25 o c -8-pf dc characteristics: i 2 c interface input logic high voltage v ih v cc = max 0.7xv cc --v input logic low voltage v il v cc = min - - 0.3xv cc v output logic high voltage v oh i oh = -1ma, v cc = max 3.0 - - v output logic low voltage v ol i ol = 3ma, v cc = min 0 - 0.4 v HMP8117 43 input leakage current i ih , i il v cc = max, input = 0v or 5v - - 10 a input/output capacitance c in , c out scl = 400khz, (note 2) all measurements referenced to gnd, t a = 25 o c -8-pf ac characteristics: digital i/o (except i 2 c interface) clk2 frequency 24.54 - 29.5 mhz clk2 waveform symmetry (note 2) 40 - 60 % clk2 pulse width high t pwh 13 - - ns clk2 pulse width low t pwl 13 - - ns data and control setup time t su (note 3) 10 - - ns data and control hold time t hd 0- -ns clk2 to output delay t dvld 0 - 23 ns data and control rise/fall time t r , t f (note 2) 1 - 12 ns ac characteristics: i 2 c interface scl clock frequency f scl 0 - 400 khz scl pulse width low t low 1.3 - - s scl pulse width high t high 0.6 - - s data hold time t hd:data 0- -ns data setup time t su:data 100 - - ns sda, scl rise time t r (note 2) - - 300 ns sda, scl fall time t f - - 300 ns analog input performance composite video input amplitude (sync tip to white level) input termination of 75 ? and 1.0 f ac- coupled 0.5 1.0 2.0 v p-p luminance (y) video input amplitude (sync tip to white level) input termination of 75 ? and 1.0 f ac- coupled 0.5 1.0 2.0 v p-p chrominance (c) video input amplitude (burst amplitude) input termination of 75 ? and 1.0 f ac- coupled, (note 2) 0.143 0.286 0.6 v p-p video input impedance r ain (note 2) 200 - - k ? video input bandwidth bw 1v p-p sine wave input to -3dbc reduction, (note 2) 5- -mhz adc input range a in full scale - 1 - v p-p a in offset - 1.5 - v adc integral nonlinearity inl best fit linearity - 2-lsb adc differential nonlinearity dnl - 0.35 - lsb video performance differential gain dg modulated ramp (note 2) - 2 - % differential phase dp - 1 - deg. hue accuracy 75% color bars (note 2) - 2 - deg. color saturation accuracy -2-% luminance nonlinearity ntc-7 composite (note 2) - 2 - % snr snrl weighted pedestal input (note 2) - 50 - db electrical specifications v cc = v aa = 5.0v, t a = 25 o c (continued) parameter symbol test condition min typ max units HMP8117 44 genlock performance horizontal locking time t lock time from initial lock acquisition to an error of 1 pixel. (note 2) 2 3 - fields long-term horizontal sync lock range range over specified pixel jitter is maintained. assumes line time changes by amount indicated slowly between over one field. (note 2) - - 5 % number of missing horizontal syncs before lost lock declared h sync lost programmable via register 04 h (note 2) 1 or 12 1 or 12 1 or 12 hsyncs number of missing vertical syncs before lost lock declared v sync lost 1 or 3 1 or 3 1 or 3 vsyncs long-term color subcarrier lock range range over color subcarrier locking time and accuracy specifications are maintained. subcarrier frequency changes by amount indicated slowly over 24 hours. (note 2) - 200 400 hz vertical sample alignment (notes 2, 4) - 1/8 - pixel -10-ns notes: 41. guaranteed by design or characterization. 42. test performed with c l = 40pf, i ol = 4ma, i oh = -4ma. input reference level is 1.5v for all inputs. v ih = 3.0v, v il = 0v. 43. since the HMP8117 does not generate the sample clock, any cloc k jitter present on the clk2 input will directly translate to pixel jitter on the output data. the vertical sample alignment parameter specifies the spatial pixel alignment from one scan line to the next using a stable clk2 source. electrical specifications v cc = v aa = 5.0v, t a = 25 o c (continued) parameter symbol test condition min typ max units HMP8117 45 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HMP8117 metric plastic quad flatpack packages (mqfp) d d1 e e1 -a- pin 1 a2 a1 a 12 o -16 o 12 o -16 o 0 o -7 o 0.40 0.016 min l 0 o min plane b 0.005/0.009 0.13/0.23 with plating base metal seating 0.005/0.007 0.13/0.17 b1 -b- e 0.008 0.20 a-b s d s c m 0.076 0.003 -c- -d- -h- q80.14x20 (jedec ms-022gb-1 issue b) 80 lead metric plastic quad flatpack package symbol inches millimeters notes min max min max a - 0.134 - 3.40 - a1 0.010 - 0.25 - - a2 0.098 0.114 2.50 2.90 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - d 0.908 0.918 23.08 23.32 3 d1 0.782 0.792 19.88 20.12 4, 5 e 0.673 0.681 17.10 17.30 3 e1 0.547 0.555 13.90 14.10 4, 5 l 0.029 0.040 0.73 1.03 - n80 807 e 0.032 bsc 0.80 bsc - nd 24 24 - ne 16 16 - rev. 1 4/99 notes: 1. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 2. all dimensions and toleranc es per ansi y14.5m-1982. 3. dimensions d and e to be determined at seating plane . 4. dimensions d1 and e1 to be determined at datum plane . 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm (0.010 inch) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. ?n? is the number of terminal positions. -c- -h- |
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